ADC08D1520DEV/NOPB National Semiconductor, ADC08D1520DEV/NOPB Datasheet - Page 9

• Manufacturer Part Number: ADC08D1520DEV/NOPB
• Description: BOARD DEV FOR ADC08D1520
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1520DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1520
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1520DEV

STATIC CONVERTER CHARACTERISTICS
INL
DNL
V
V
PFSE
NFSE
FS_ADJ
1:2 DEMUX NON-DES MODE, DYNAMIC CONVERTER CHARACTERISTICS; F
FPBW
C.E.R.
ENOB
SINAD
OFF
OFF
Absolute Maximum Ratings
(Note
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Converter Electrical Characteristics
The following specifications apply after calibration for V
mV
Non-extended Control Mode; SDR Mode; R
Demultiplex Mode; Duty Cycle Stabilizer on. Boldface limits apply for T
otherwise noted.
Symbol
Supply Voltage (V
Supply Difference
Voltage on Any Input Pin
(Except V
Voltage on V
(Maintaining Common Mode)
Ground Difference
Input Current at Any Pin
Package Input Current
Power Dissipation at T
ESD Susceptibility
Storage Temperature
_ADJ
P-P
|GND - DR GND|
Human Body Model
Machine Model
Charged Device Model
V
1,
; C
DR
Note
L
= 10 pF; Differential, a.c. coupled Sine Wave Input Clock, f
- V
IN
Integral Non-Linearity
(Best fit)
Differential Non-Linearity
Resolution with No Missing
Codes
Offset Error
Input Offset Adjustment Range Extended Control Mode
Positive Full-Scale Error
Negative Full-Scale Error
Full-Scale Adjustment Range
Full Power Bandwidth
Code Error Rate
Gain Flatness
Effective Number of Bits
Signal-to-Noise Plus Distortion
Ratio
+, V
A
IN
2)
+, V
IN
(Note
- )
A
IN
, V
(Note
-
Parameter
DR
6,
A
(Note
)
≤
(Note
Note
4)
85°C
3)
7,
3)
Note
−0.15V to (V
16)
−65°C to +150°C
EXT
DC Coupled, 1 MHz Sine Wave Over-
ranged
DC Coupled, 1 MHz Sine Wave Over-
ranged
(Note
(Note
Extended Control Mode
Non-DES Mode
d.c. to 748 MHz
d.c. to 1.5 GHz
f
f
f
f
-0.15V to 2.5V
IN
IN
IN
IN
0V to 100 mV
0V to 100 mV
= 373 MHz, V
= 748 MHz, V
= 373 MHz, V
= 748 MHz, V
= 3300 Ω ±0.1%; Analog Signal Source Impedance = 100 Ω Differential; 1:2
A
9)
9)
+0.15V)
±25 mA
±50 mA
2.35 W
2500V
1000V
250V
2.2V
A
= V
Conditions
DR
IN
IN
IN
IN
= FSR − 0.5 dB
= FSR − 0.5 dB
= FSR − 0.5 dB
= FSR − 0.5 dB
= +1.9V; OutV = 1.9V; V
9
CLK
Operating Ratings
Soldering
Semiconductor’s Reflow Temperature Profile specifications.
Refer to www.national.com/packaging.
Ambient Temperature Range
Supply Voltage (V
Driver Supply Voltage (V
Analog Input Common Mode Voltage
V
(Maintaining Common Mode)
Ground Difference
CLK Pins Voltage Range
Differential CLK Amplitude
Exposed Pad LQFP
IN
= 1.5 GHz at 0.5 V
+, V
A
(|GND - DR GND|)
128-Lead,
= T
Package
IN
- Voltage Range
MIN
CLK
process
to T
Package Thermal Resistance
= 1.5 GHZ
MAX
A
IN
)
(Note
Typical
P-P
. All other limits T
FSR (a.c. coupled) = differential 870
±0.15
−0.75
10
±0.3
±0.5
±1.0
46.5
46.4
±45
±20
2.0
7.4
7.4
with 50% duty cycle; V
−18
must
26°C / W
DR
8)
)
θ
JA
(Note
comply
(Note
Limits
±0.9
±0.6
42.5
±25
±25
±15
6.8
Package
10°C / W
8
−40°C
Top of
A
1,
(Note
θ
= 25°C, unless
8)
Note
(100% duty cycle)
0.4V
JC
(10% duty cycle)
with
+1.8V to +2.0V
5)
≤
V
P-P
2)
BG
CMO
0V to 2.15V
T
+1.8V to V
www.national.com
Error/Sample
0V to 2.5V
A
to 2.0V
= Floating;
2.8°C / W
LSB (max)
LSB (max)
mV (max)
mV (max)
Thermal
Bits (min)
≤
0V to V
dB (min)
(Limits)
±50 mV
National
Units
dBFS
dBFS
Pad
%FS
+85°C
GHz
LSB
θ
Bits
Bits
mV
dB
JC
0V
P-P
A
A