ADC08D1520DEV/NOPB National Semiconductor, ADC08D1520DEV/NOPB Datasheet - Page 27

• Manufacturer Part Number: ADC08D1520DEV/NOPB
• Description: BOARD DEV FOR ADC08D1520
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1520DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1520
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1520DEV

inputs with the V
V
to the V
input voltage to V
Two full-scale range settings are provided via pin 14 (FSR).
In Non-extended Control Mode, a logic high on pin 14 causes
an input full-scale range setting of a normal V
while a logic low on pin 14 causes an input full-scale range
setting of a reduced V
ting operates on both ADCs.
In the Extended Control Mode, programming the Input Full-
Scale Voltage Adjust register allows the input full-scale range
to be adjusted as described in
TION
1.1.5 Clocking
The ADC08D1520 must be driven with an a.c. coupled, dif-
ferential clock signal.
use of the clock input pins. A differential LVDS output clock is
available for use in latching the ADC output data into whatever
device is used to receive the data.
The ADC08D1520 offers output clocking options: two of these
options are Single Data Rate (SDR) and Double Data Rate
(DDR). In SDR mode, the user has a choice of which Data
Clock (DCLK) edge, rising or falling, the output data transi-
tions on.
The ADC08D1520 also has the option to use a duty cycle
corrected clock receiver as part of the input clock circuit. This
feature is enabled by default and provides improved ADC
clocking, especially in the Dual-Edge Sampling (DES) Mode.
This circuitry allows the ADC to be clocked with a signal
source having a duty cycle ratio of 20%/80% (worst case) for
both the Non-DES and the DES Modes.
* Note that, in DES Mode and Non-extended Control Mode, only the I-channel is sampled. In DES Mode and Extended Control Mode, the I- or Q-channel can be
sampled.
** Note that, in the Non-demux Mode (DES and Non-DES Mode), the DId and DQd outputs are disabled and are high impedance.
CMO
respect to fall of DCLK+)
(Always sourced with
pin left floating. An input common mode voltage equal
and
CMO
Data Outputs
2.2 THE ANALOG
output must be provided as the common mode
DQd
DId
DQ
DI
CMO
TABLE 1. Input Channel Samples Produced at Data Outputs in 1:2 Demultiplexed Mode**
IN
+ and V
(pin 7) grounded, or d.c. coupled with the
2.3 THE CLOCK INPUTS
IN
input level. The full-scale range set-
IN
- when d.c. coupling is used.
INPUT.
I-channel sampled with fall of CLK,
13 cycles earlier.
I-channel sampled with fall of CLK,
14 cycles earlier.
Q-channel sampled with fall of CLK,
13 cycles earlier.
Q-channel sampled with fall of CLK,
14 cycles earlier.
1.4 REGISTER DESCRIP-
Non-DES Sampling Mode
IN
describes the
input level,
27
I-channel sampled with fall
of CLK,
13 cycles earlier.
I-channel sampled with fall
of CLK,
14 cycles earlier.
I-channel sampled with rise
of CLK,
13.5 cycles earlier.
I-channel sampled with rise
of CLK,
14.5 cycles earlier.
1.1.5.1 Dual-Edge Sampling
The Dual-Edge Sampling (DES) Mode allows either of the
ADC08D1520's inputs (I- or Q-channel) to be sampled by both
ADCs. One ADC samples the input on the rising edge of the
input clock and the other ADC samples the same input on the
falling edge of the input clock. A single input is thus sampled
twice per input clock cycle, resulting in an overall sample rate
of twice the input clock frequency, or 3 GSPS with a 1.5 GHz
input clock.
In this mode, the outputs must be carefully interleaved to re-
construct the sampled signal. If the device is programmed into
the 1:4 Demux DES Mode, the data is effectively demulti-
plexed by 1:4. If the input clock is 1.5 GHz, the effective
sampling rate is doubled to 3 GSPS and each of the 4 output
buses has an output rate of 750 MHz. All data is available in
parallel. To properly reconstruct the sampled waveform, the
four bytes of parallel data that are output with each clock are
in the following sampling order, from the earliest to the latest,
and must be interleaved as such: DQd, DId, DQ, DI.
indicates what the outputs represent for the various sampling
possibilities. If the device is programmed into the Non-demux
DES Mode, two bytes of parallel data are output with each
edge of the clock in the following sampling order, from the
earliest to the latest: DQ, DI. See
In the Non-extended Control and DES Mode of operation,
only the I-channel can be sampled. In the Extended Control
Mode of operation, the user can select which input is sampled.
The ADC08D1520 also includes an automatic clock phase
background adjustment in DES Mode to automatically and
continuously adjust the clock phase of the I- and Q-channels.
This feature removes the need to adjust the clock phase set-
ting manually and provides optimal DES Mode performance.
I-Channel Selected
Dual-Edge Sampling (DES) Mode
Q-channel sampled with fall
of CLK,
13 cycles earlier.
Q-channel sampled with fall
of CLK,
14 cycles earlier.
Q-channel sampled with rise
of CLK,
13.5 cycles earlier.
Q-channel sampled with rise
of CLK,
14.5 cycles earlier.
Q-Channel Selected *
Table
2.
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Table 1