ADC08D1520DEV/NOPB National Semiconductor, ADC08D1520DEV/NOPB Datasheet - Page 38

• Manufacturer Part Number: ADC08D1520DEV/NOPB
• Description: BOARD DEV FOR ADC08D1520
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1520DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1520
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1520DEV

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Insufficient input clock levels will result in poor dynamic per-
formance. Excessively high input clock levels could cause a
change in the analog input offset voltage. To avoid this, keep
the input clock level (V
Converter Electrical Characteristics.
The low and high times of the input clock signal can affect the
performance of any A/D Converter. The ADC08D1520 fea-
tures a duty cycle clock correction circuit which can maintain
performance over the 20%-to-80% specified duty cycle
range, even in DES Mode. The ADC will meet its performance
specification if the input clock high and low times are main-
tained within the duty cycle range; see the Converter Electri-
cal Characteristics.
High speed, high performance ADCs such as the AD-
C08D1520 require a very stable input clock signal with mini-
mum phase noise or jitter. ADC jitter requirements are defined
by the ADC resolution (number of bits), maximum ADC input
frequency and the input signal amplitude relative to the ADC
input full scale range. The maximum jitter (the sum of the jitter
from all sources) allowed to prevent a jitter-induced reduction
in SNR is found to be
where t
V
full-scale range of the ADC, "N" is the ADC resolution in bits
and f
analog input.
Note that the maximum jitter described above is the RSS sum
of the jitter from all sources, including that in the ADC input
clock, that added by the system to the ADC input clock and
input signals and that added by the ADC itself. Since the ef-
fective jitter added by the ADC is beyond user control, the best
the user can do is to keep the sum of the externally added
input clock jitter and the jitter added by the analog circuitry to
the analog signal to a minimum.
Input clock amplitudes above those specified in the Converter
Electrical Characteristics may result in increased input offset
voltage. This would cause the converter to produce an output
code other than the expected 127/128 when both input pins
are at the same potential.
2.4 CONTROL PINS
Six control pins (without the use of the serial interface) provide
a wide range of possibilities in the operation of the
ADC08D1520 and facilitate its use. These control pins pro-
vide Full-Scale Input Range setting, Calibration, Calibration
Delay, Output Edge Synchronization choice, LVDS Output
Level choice and a Power Down feature.
2.4.1 Full-Scale Input Range Setting
The input full-scale range can be selected with the FSR con-
trol input (pin 14) in the Non-extended Control Mode of oper-
ation. The input full-scale range is specified as V
Converter Electrical Characteristics. In the Extended Control
Mode, the input full-scale range may be programmed using
the Full-Scale Adjust Voltage register. See
INPUT
2.4.2 Calibration
The ADC08D1520 calibration must be run to achieve speci-
fied performance. The calibration procedure is run automati-
cally upon power-up and can be run any time on-command
via the CAL pin (30) or the Calibration register (Addr: 0h, Bit
15). The calibration procedure is exactly the same whether
there is an input clock present upon power up or if the clock
IN(P-P)
IN
t
is the maximum input frequency, in Hertz, at the ADC
J(MAX)
for more information.
J(MAX)
is the peak-to-peak analog input signal, V
= ( V
is the rms total of all jitter sources in seconds,
INFSR
/ V
ID
) within the range specified in the
IN(P-P)
) x (1/(2
(N+1)
2.2 THE ANALOG
x
π
x f
INFSR
IN
IN
))
in the
is the
38
begins some time after application of power. The CalRun out-
put indicator is high while a calibration is in progress. Note
that the DCLK outputs are not active during a calibration cycle
by default, therefore it is not recommended to use these sig-
nals as a system clock unless the Resistor Trim Disable
feature is used (Reg. 9h). The DCLK outputs are continuously
present at the output only when the Resistor Trim Disable is
active.
2.4.2.1 Power-On Calibration
Power-on calibration begins after a time delay following the
application of power. This time delay is determined by the
setting of CalDly.
The calibration process will be not be performed if the CAL
pin is high at power up. In this case, the calibration cycle will
not begin until the on-command calibration conditions are
met. The ADC08D1520 will function with the CAL pin held
high at power up, but no calibration will be done and perfor-
mance will be impaired. A manual calibration, however, may
be performed after powering up with the CAL pin high. See
2.4.2.2 On-Command
The internal power-on calibration circuitry comes up in an un-
known logic state. If the input clock is not running at power up
and the power on calibration circuitry is active, it will hold the
analog circuitry in power down and the power consumption
will typically be less than 200 mW. The power consumption
will be normal after the clock starts.
2.4.2.2 On-Command Calibration
To initiate an on-command calibration, either bring the CAL
pin high for a minimum of t
been low for a minimum of t
the same operation via the CAL bit in the Calibration register.
Holding the CAL pin high upon power up will prevent execu-
tion of power-on calibration until the CAL pin is low for a
minimum of t
minimum of another t
cycle will begin t
thus brought high. The CalRun signal should be monitored to
determine when the calibration cycle has completed.
The minimum t
are required to ensure that random noise does not cause a
calibration to begin when it is not desired. For best perfor-
mance, a calibration should be performed 20 seconds or more
after power up and repeated when the operating temperature
changes significantly, relative to the specific system design
performance requirements.
By default, on-command calibration also includes calibrating
the input termination resistance and the ADC. However, since
the input termination resistance, once trimmed at power-up,
changes marginally with temperature, the user has the option
to disable the input termination resistor trim, which will guar-
antee that the DCLK is continuously present at the output
during subsequent calibration. The Resistor Trim Disable
(RTD) can be programmed in register 9h when in the Extend-
ed Control Mode. Refer to
register programming information.
2.4.2.3 Calibration Delay
The CalDly input (pin 127) is used to select one of two delay
times after the application of power to the start of calibration,
as described in
allow the power supply to come up and stabilize before cali-
bration takes place. With no delay or insufficient delay, cali-
bration would begin before the power supply is stabilized at
its operating value and result in non-optimal calibration coef-
CAL_L
CAL_L
1.1.1
CAL_H
input clock cycles, then brought high for a
and t
Calibration. The calibration delay values
CAL_H
Calibration.
input clock cycles after the CAL pin is
CAL_H
1.4 REGISTER DESCRIPTION
CAL_H
CAL_L
input clock cycles. The calibration
input clock cycles after it has
input clock cycle sequences
input clock cycles or perform
for