ADC08D1520DEV/NOPB National Semiconductor, ADC08D1520DEV/NOPB Datasheet - Page 33

• Manufacturer Part Number: ADC08D1520DEV/NOPB
• Description: BOARD DEV FOR ADC08D1520
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1520DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1520
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1520DEV

Bit 15:7
Bits 6:0
Bit 15
Bit 14
Bit 13
(MSB)
Addr: 3h (0011b)
Addr: 9h (1001b)
(LSB)
TPO RTD DEN
D15
D15
D7
D7
1
D14
I-Channel Full-Scale Voltage Adjust
D6
D14
1
D6
Extended Configuration Register
Full Scale Voltage Adjust Value. The input full-
scale voltage or gain of the I-channel is
adjusted linearly and monotonically with a 9 bit
data value. The adjustment range is ±20% of
the nominal 700 mV
0000 0000 0
1000 0000 0
Default Value
1111 1111 1
For best performance, it is recommended that
the value in this field be limited to the range of
0110 0000 0b to 1110 0000 0b, i.e., limit the
amount of adjustment to ±15%. The remaining
±5% headroom allows for the ADC's own full
scale variation. A gain adjustment does not
require ADC re-calibration.
POR State: 1000 0000 0b (no adjustment)
Must be set to 1b
1
TPO: Test Pattern Output. When this bit is set
1b, the ADC is disengaged and a test pattern
generator is connected to the outputs
including OR. This test pattern will work with
the device in the SDR, DDR and the Non-
demux Modes (DES and Non-DES).
POR State: 0b
RTD: Resistor Trim Disable. When this bit is
set to 1b, the input termination resistor is not
trimmed during the calibration cycle and the
DCLK output remains enabled. Note that the
ADC is calibrated regardless of this setting.
POR State: 0b
DEN: DES Enable. Setting this bit to 1b
enables the Dual Edge Sampling Mode. In
this mode, the ADCs in this device are used
to sample and convert the same analog input
in a time-interleaved manner, accomplishing
a sample rate of twice the input clock rate.
When this bit is set to 0b, the device operates
in the Non-DES Modes.
POR State: 0b
D13
D5
D13
1
D5
1
D12
D4
IS
D12
1
D4
1
Adjust Value
D11
560mV
700mV
840mV
D3
D11
0
1
P-P
D3
1
Write only (0x03FF)
Write only (0x807F)
differential value.
DLF
D10
P-P
P-P
P-P
D2
D10
1
D2
1
D9
D1
1
1
D9
D1
1
D8
D0
1
1
D8
D0
1
33
Bit 15:8
Bit 7
Bit 6:0
Bit 15:7
Bits 6:0
Bit 12
Bit 11
Bit 10
Bits 9:0
(MSB)
Addr: Ah (1010b)
Addr: Bh (1011b)
(MSB)
(LSB)
Sign
D15
D15
D7
D7
Q-Channel Full-Scale Voltage Adjust
D14
D6
D14
1
D6
Offset Value. The input offset of the Q-channel
ADC is adjusted linearly and monotonically by
the value in this field. 00h provides a nominal
zero offset, while FFh provides a nominal 45
mV of offset. Thus, each code step provides
about 0.176 mV of offset.
POR State: 0000 0000 b
Sign bit. 0b gives positive offset, 1b gives
negative offset.
POR State: 0b
Must be set to 1b
Full Scale Voltage Adjust Value. The input full-
scale voltage or gain of the Q-channel ADC is
adjusted linearly and monotonically with a 9 bit
data value. The adjustment range is ±20% of
the nominal 700 mV
0000 0000 0
1000 0000 0
1111 1111 1
For best performance, it is recommended that
the value in this field be limited to the range of
0110 0000 0b to 1110 0000 0b, i.e., limit the
amount of adjustment to ±15%. The remaining
±5% headroom allows for the ADC's own full
scale variation. A gain adjustment does not
require ADC re-calibration.
POR State: 1000 0000 0b (no adjustment)
Must be set to 1b
1
IS: Input Select. When this bit is set to 0b the
I-channel is operated upon by both ADCs.
When this bit is set to 1b the Q-channel is
operated on by both ADCs.
POR State: 0b
Must be set to 0b
DLF: DES Low Frequency. When this bit is
set 1b, the dynamic performance of the
device is improved when the input clock is
less than 900 MHz.
POR State: 0b
Must be set to 1b
D13
D5
D13
1
D5
1
Q-Channel Offset
Offset Value
D12
D4
1
D12
D4
1
Adjust Value
D11
560 mV
700 mV
840 mV
D3
D11
1
P-P
D3
1
Write only (0x007F)
Write only (0x807F)
differential value.
D10
D2
P-P
P-P
P-P
D10
1
D2
1
D9
D1
1
D9
D1
1
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(LSB)
D8
D0
1
D8
D0
1