ADC08D1520DEV/NOPB National Semiconductor, ADC08D1520DEV/NOPB Datasheet - Page 42

• Manufacturer Part Number: ADC08D1520DEV/NOPB
• Description: BOARD DEV FOR ADC08D1520
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1520DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1520
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1520DEV

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(Pin 41 Logic Low or Pin 14 Floating and Pin 52 Floating
2.10 COMMON APPLICATION PITFALLS
Failure to write all register locations when using extend-
ed control mode. When using the serial interface, all nine
address locations must be written at least once with the de-
fault or desired values before calibration and subsequent use
of the ADC.
Driving the inputs (analog or digital) beyond the power
supply rails. For device reliability, no input should go more
than 150 mV below the ground pins or 150 mV above the
supply pins. Exceeding these limits on even a transient basis
may not only cause faulty or erratic operation, but may impair
device reliability. It is not uncommon for high speed digital
circuits to exhibit undershoot that goes more than a volt below
ground. Controlling the impedance of high speed lines and
terminating these lines in their characteristic impedance
should control overshoot.
Care should be taken not to overdrive the inputs of the
ADC08D1520. Such practice may lead to conversion inaccu-
racies and even to device damage.
Incorrect analog input common mode voltage in the d.c.
coupled mode. As discussed in
2.2 THE ANALOG
must remain within 50 mV of the V
with temperature and must also be tracked. Distortion perfor-
mance will be degraded if the input common mode voltage is
more than 50 mV from V
TABLE 11. Extended Control Mode Operation
127
Pin
3
4
INPUT, the Input common mode voltage
or Logic High)
SCS (Serial Interface Chip Select)
CMO
.
SDATA (Serial Data)
SCLK (Serial Clock)
1.1.4 The Analog Inputs
CMO
Function
output , which varies
and
42
Using an inadequate amplifier to drive the analog input.
Use care when choosing a high frequency amplifier to drive
the ADC08D1520 as many high speed amplifiers will have
higher distortion than the ADC08D1520, resulting in overall
system performance degradation.
Driving the V
mentioned in
ence voltage is intended to be fixed by FSR pin or Full-Scale
Voltage Adjust register settings. Over driving this pin will not
change the full scale value, but can be used to change the
LVDS common mode voltage from 0.8V to 1.2V by tying the
V
Driving the clock input with an excessively high level
signal. The ADC input clock level should not exceed the level
described in the Operating Ratings Table or the input offset
could change.
Inadequate input clock levels. As described in
CLOCK
poor performance. Excessive input clock levels could result
in the introduction of an input offset.
Using a clock source with excessive jitter, using an ex-
cessively long input clock signal trace, or having other
signals coupled to the input clock signal trace. This will
cause the sampling interval to vary, causing excessive output
noise and a reduction in SNR performance.
Failure to provide adequate heat removal. As described in
2.6.2 Thermal
quate heat removal to ensure device reliability. This can be
done either with adequate air flow or the use of a simple heat
sink built into the board. The backside pad should be ground-
ed for best performance.
BG
pin to V
INPUTS, insufficient input clock levels can result in
A
.
BG
2.1 THE REFERENCE
Management, it is important to provide ade-
pin to change the reference voltage. As
VOLTAGE, the refer-
2.3 THE