ADC08D1520DEV/NOPB National Semiconductor, ADC08D1520DEV/NOPB Datasheet
ADC08D1520DEV/NOPB
Specifications of ADC08D1520DEV/NOPB
Related parts for ADC08D1520DEV/NOPB
ADC08D1520DEV/NOPB Summary of contents
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... Industrial (-40°C T range. Ordering Information Industrial Temperature Range (-40°C < T ADC08D1520CIYB ADC08D1520CIYB/NOPB ADC08D1520DEV © 2009 National Semiconductor Corporation ADC08D1520 Features ■ Single +1.9V ±0.1V Operation ■ Interleave Mode for 2x Sample Rate ■ Multiple ADC Synchronization Capability ■ ...
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Block Diagram www.national.com 2 20193153 ...
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Pin Configuration Note: The exposed pad on the bottom of the package must be soldered to a ground plane to ensure rated performance. 3 20193101 www.national.com ...
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Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol 3 OutV / SCLK 29 PDQ OutEdge / DDR / 4 SDATA DCLK_RST / 15 DCLK_RST CAL www.national.com Equivalent Circuit Output Voltage Amplitude and Serial Interface Clock. ...
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Pin Functions Pin No. Symbol FSR/ALT_ECE/ 14 DCLK_RST- 127 CalDly / DES / SCS 18 CLK+ 19 CLK Q− IN Equivalent Circuit Full Scale Range Select, ...
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Pin Functions Pin No. Symbol 7 V CMO 126 CalRun R 32 EXT 34 Tdiode_P 35 Tdiode_N 41 ECE 52 DRST_SEL www.national.com Equivalent Circuit Common Mode Voltage. This pin is the common mode output in d.c. coupling ...
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Pin Functions Pin No. Symbol DI7− / DQ7− DI7+ / DQ7 DI6− / DQ6− DI6+ / DQ6 DI5− / DQ5− DI5+ / ...
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Pin Functions Pin No. Symbol 81 DCLK- 82 DCLK 13, 16, 17, 20 25, 28, 33, 128 40, 51, 62, V 73, 88, 99, DR 110, 121 12, GND 21, 24, 27 ...
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... Absolute Maximum Ratings (Note 1, Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Supply Difference Voltage on Any Input Pin (Except Voltage (Maintaining Common Mode) Ground Difference |GND - DR GND| Input Current at Any Pin ...
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Symbol Parameter SNR Signal-to-Noise Ratio THD Total Harmonic Distortion 2nd Harm Second Harmonic Distortion 3rd Harm Third Harmonic Distortion SFDR Spurious-Free Dynamic Range IMD Intermodulation Distortion Out of Range Output Code NON-DEMUX NON-DES MODE, DYNAMIC CONVERTER CHARACTERISTICS; F ENOB Effective ...
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Symbol Parameter Analog Input Capacitance, Normal operation (Note 10, Note 11 Analog Input Capacitance, DES Mode (Note 10, Note R Differential Input Resistance IN ANALOG OUTPUT CHARACTERISTICS V Common Mode Output Voltage I CMO Common Mode Output Voltage ...
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Symbol Parameter DIGITAL OUTPUT CHARACTERISTICS LVDS Differential Output V OD Voltage Change in LVDS Output Swing ΔV O DIFF Between Logic Levels Output Offset Voltage V OS See Figure 1 Output Offset Voltage Change ΔV OS Between Logic Levels I ...
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Symbol Parameter A.C. ELECTRICAL CHARACTERISTICS Maximum Input Clock f CLK (max) Frequency Minimum Input Clock f CLK (min) Frequency Input Clock Duty Cycle t Input Clock Low Time CL t Input Clock High Time CH DCLK Duty Cycle t Setup ...
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Symbol Parameter CS to Serial Clock Falling Hold t HCS Time Serial Clock Low Time Serial Clock High Time t Calibration Cycle Time CAL t CAL Pin Low Time CAL_L t CAL Pin High Time CAL_H Calibration delay determined t ...
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Specification Definitions APERTURE (SAMPLING) DELAY is the amount of delay, measured from the sampling edge of the CLK input, after which the signal present at the input pin is sampled inside the device the variation in aperture delay ...
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SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of all of the other spectral components below half the input ...
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Transfer Characteristic FIGURE 2. Input / Output Transfer Characteristic 17 20193122 www.national.com ...
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Timing Diagrams FIGURE 3. SDR Clocking in 1:2 Demultiplexed Non-DES Mode FIGURE 4. DDR Clocking in 1:2 Demultiplexed Non-DES Mode www.national.com 18 20193114 20193159 ...
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FIGURE 5. DDR Clocking in Non-Demultiplexed Non-DES Mode FIGURE 6. Serial Interface Timing FIGURE 7. Clock Reset Timing in DDR Mode 19 20193160 20193119 20193120 www.national.com ...
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FIGURE 8. Clock Reset Timing in SDR Mode with OUTEDGE Low FIGURE 9. Clock Reset Timing in SDR Mode with OUTEDGE High FIGURE 10. Power-on and On-Command Calibration Timing www.national.com 20 20193123 20193124 20193125 ...
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Typical Performance Characteristics channel, 1:2 Demux Mode (1:1 Demux Mode has similar performance), unless otherwise stated. INL vs. CODE DNL vs. CODE POWER CONSUMPTION vs. CLOCK FREQUENCY 1.9V 1500 MHz CLK ...
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ENOB vs. SUPPLY VOLTAGE ENOB vs. INPUT FREQUENCY SNR vs. SUPPLY VOLTAGE www.national.com ENOB vs. CLOCK FREQUENCY 20193177 SNR vs. TEMPERATURE 20193179 SNR vs. CLOCK FREQUENCY 20193169 22 20193178 20193168 20193170 ...
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SNR vs. INPUT FREQUENCY 20193171 THD vs. SUPPLY VOLTAGE 20193173 THD vs. INPUT FREQUENCY 20193175 THD vs. TEMPERATURE THD vs. CLOCK FREQUENCY SFDR vs. TEMPERATURE 23 20193172 20193174 20193185 www.national.com ...
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SFDR vs. SUPPLY VOLTAGE SFDR vs. INPUT FREQUENCY Spectral Response at FIN = 748 MHz www.national.com SFDR vs. CLOCK FREQUENCY 20193184 Spectral Response at FIN = 373 MHz 20193183 CROSSTALK vs. SOURCE FREQUENCY 20193188 24 20193182 20193187 20193163 ...
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FULL POWER BANDWIDTH (NON-DES MODE) GAIN STABILITY vs. DIE TEMPERATURE 20193186 25 20193195 www.national.com ...
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Functional Description The ADC08D1520 is a versatile A/D Converter with an inno- vative architecture permitting very high speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed ...
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V (pin 7) grounded, or d.c. coupled with the CMO V pin left floating. An input common mode voltage equal CMO to the V output must be provided as the common mode CMO input voltage to V ...
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TABLE 2. Input Channel Samples Produced at Data Outputs in Non-Demux Mode Data Outputs (Always sourced with Non-DES Sampling Mode respect to fall of DCLK+) I-channel sampled with fall of CLK cycles earlier. No output; DId high impedance. ...
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The LVDS Outputs The Data, Out Of Range (OR+/-), and Data Clock (DCLK+/-) outputs are LVDS. The electrical specifications of the LVDS outputs are compatible with typical LVDS receivers available on ASIC and FPGA chips; but they are not ...
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Dual Edge Sampling Selection Dual Edge Sampling Input Channel Selection Test Pattern Resistor Trim Disable Selectable Output Demultiplexer Second DCLK Output Sampling Clock Phase Adjust The default state of the Extended Control Mode is set upon power-on reset (internally performed ...
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THE SERIAL INTERFACE IMPORTANT NOTE: During the initial write using the serial interface, all nine registers must be written with desired or default values. Subsequent writes to single registers are al- lowed. The 3-pin serial interface is enabled only ...
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Configuration Register Addr: 1h (0001b) D15 D14 D13 D12 D11 1 0 nSD DCS DCP Bit 15 Must be set to 1b Bit 14 Must be set to 0b Bit ...
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I-Channel Full-Scale Voltage Adjust Addr: 3h (0011b) Write only (0x807F) D15 D14 D13 D12 D11 D10 (MSB) Adjust Value (LSB Bit 15:7 Full Scale Voltage Adjust Value. The input full- ...
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Sample Clock Phase Fine Adjust Addr: Eh (1110b) D15 D14 D13 D12 D11 (MSB) Fine Phase Adjust Bits 15:8 Fine Phase Adjust. The phase of the ADC sampling clock is ...
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TABLE 6. Test Pattern by Output Port in 1:2 Demultiplex Mode Time 01h 02h 03h 04h T1 FEh FDh FCh FBh T2 01h 02h 03h 04h T3 FEh FDh FCh FBh T4 01h 02h 03h ...
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IMPORTANT NOTE: An analog input channel that is not used (e.g. in DES Mode) should be connected to a.c. ground (i.e., capacitors to ground) when the inputs are a.c. coupled. Do not connect an unused analog input directly to ground. ...
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FIGURE 13. Example of Using LM6555 for D.C. Coupled Input In Figure 13, R and R are used to adjust the differential ADJ- ADJ+ offset that can be measured at the ADC inputs V with the LMH6555's input terminated to ...
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Insufficient input clock levels will result in poor dynamic per- formance. Excessively high input clock levels could cause a change in the analog input offset voltage. To avoid this, keep the input clock level (V ) within the range specified ...
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If the PD pin is high upon power-up, the calibration delay counter will be disabled until the PD pin is brought low. Therefore, holding the PD pin high during power up will further delay the start of the power-up ...
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As is the case with all high speed converters, the ADC08D1520 should be assumed to have little power supply noise rejection. Any power supply used for digital circuitry in a system where a lot of digital power is being consumed ...
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The thermal vias should be placed on a 1.2 mm grid spacing and have a diameter of 0.30 to 0.33 mm. These vias should be barrel plated to avoid solder wicking into the vias during the soldering process as this ...
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TABLE 11. Extended Control Mode Operation (Pin 41 Logic Low or Pin 14 Floating and Pin 52 Floating or Logic High) Pin 3 SCLK (Serial Clock) 4 SDATA (Serial Data) 127 SCS (Serial Interface Chip Select) 2.10 COMMON APPLICATION PITFALLS ...
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Physical Dimensions inches (millimeters) unless otherwise noted NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB. 128-Lead Exposed Pad LQFP Order Number ADC08D1520CIYB NS Package Number VNX128A 43 www.national.com ...
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