ADC08D1520DEV/NOPB National Semiconductor, ADC08D1520DEV/NOPB Datasheet - Page 41

• Manufacturer Part Number: ADC08D1520DEV/NOPB
• Description: BOARD DEV FOR ADC08D1520
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1520DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1520
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1520DEV

The thermal vias should be placed on a 1.2 mm grid spacing
and have a diameter of 0.30 to 0.33 mm. These vias should
be barrel plated to avoid solder wicking into the vias during
the soldering process as this wicking could cause voids in the
solder between the package exposed pad and the thermal
land on the PCB. Such voids could increase the thermal re-
sistance between the device and the thermal land on the
board, which would cause the device to run hotter.
If it is desired to monitor die temperature, a temperature sen-
sor may be mounted on the heat sink area of the board near
the thermal vias. Allow for a thermal gradient between the
temperature sensor and the ADC08D1520 die of θ
typical power consumption = 2.8°C/W x 1.8W = 5°C. Allowing
for 6°C, including some margin for temperature drop from the
pad to the temperature sensor, would mean that maintaining
a maximum pad temperature reading of 124°C will ensure that
the die temperature does not exceed 130°C. This calculation
assumes that the exposed pad of the ADC08D1520 is prop-
erly soldered down and the thermal vias are adequate. (The
inaccuracy of the temperature sensor is in addition to the
above calculation).
2.7 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essen-
tial to ensure accurate conversion. A single ground plane
should be used, instead of splitting the ground plane into ana-
log and digital areas.
Since digital switching transients are composed largely of
high frequency components, the skin effect implies that the
total ground plane copper weight will have little effect upon
the logic-generated noise. Total surface area is more impor-
tant than is total ground plane volume. Coupling between the
typically noisy digital circuitry and the sensitive analog circuit-
ry can lead to poor performance that may seem impossible to
isolate and remedy. The solution is to keep the analog cir-
cuitry well separated from the digital circuitry.
High power digital components should not be located on or
near any linear component or power supply trace or plane that
services analog or mixed signal components, as the resulting
common return current path could cause fluctuation in the
analog input “ground” return of the ADC, causing excessive
noise in the conversion result.
Generally, it is assumed that analog and digital lines should
cross each other at 90° to avoid getting digital noise into the
analog path. In high frequency systems, however, avoid
crossing analog and digital lines altogether. The input clock
lines should be isolated from ALL other lines, analog AND
digital. The generally accepted 90° crossing should be avoid-
ed, as even a little coupling can cause problems at high
frequencies. Best performance at high frequencies is ob-
tained with a straight signal path.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. This is
especially important with the low level drive required of the
ADC08D1520. Any external component (e.g., a filter capaci-
tor) connected between the converter's input and ground
should be connected to a very clean point in the analog
ground plane. All analog circuitry (input amplifiers, filters, etc.)
should be separated from any digital components.
2.8 DYNAMIC PERFORMANCE
The ADC08D1520 is a.c. tested and its dynamic performance
is guaranteed. To meet the published specifications and avoid
jitter-induced noise, the clock source driving the CLK input
must exhibit low rms jitter. The allowable jitter is a function of
J-PAD
times
41
the input frequency and the input signal level, as described in
2.3 THE CLOCK
It is good practice to keep the ADC input clock line as short
as possible, to keep it well away from any other signals and
to treat it as a transmission line. Other signals can introduce
jitter into the input clock signal. The clock signal can also in-
troduce noise into the analog path if not isolated from that
path.
Best dynamic performance is obtained when the exposed pad
at the back of the package has a good connection to ground.
This is because this path from the die to ground is a lower
impedance than offered by the package pins.
2.9 USING THE SERIAL INTERFACE
The ADC08D1520 may be operated in the Non-extended
Control Mode or in the Extended Control Mode.
Table 11
Non-extended Control Mode and the Extended Control Mode,
respectively.
2.9.1 Non-Extended Control Mode Operation
Non-extended Control Mode operation means that the Serial
Interface is not active and all controllable functions are con-
trolled with various pin settings. Pin 41 is the primary control
of the Extended Control Mode enable function. When pin 41
is logic high, the device is in the Non-extended Control Mode.
If pin 41 is floating and pin 52 is floating or logic high, the
Extended Control Enable function is controlled by pin 14. The
device has functions which are pin programmable when in the
Non-extended Control Mode. An example is the full-scale
range; it is controlled in the Non-extended Control Mode by
setting pin 14 logic high or low.
functions of the ADC08D1520 in the Non-extended Control
Mode.
Pin 3 can be either logic high or low in the Non-extended
Control Mode. Pin 14 must not be left floating to select this
mode. See
TROL MODE
Pin 4 can be logic high, logic low or left floating in the Non-
extended Control Mode. In the Non-extended Control Mode,
pin 4 logic high or low defines the edge at which the output
data transitions. See
more information. If this pin is floating, the output Data Clock
(DCLK) is a Double Data Rate (DDR) clock (see
ble Data Rate and Single Data
synchronization is irrelevant since data is clocked out on both
DCLK edges.
Pin 127, if it is logic high or low in the Non-extended Control
Mode, sets the calibration delay. If pin 127 is floating, the cal-
ibration delay is short and the converter performs in DES
Mode.
127
(Pin 41 Floating and Pin 52 Floating or Logic High)
Pin
TABLE 10. Non-Extended Control Mode Operation
14
3
4
describe the functions of pins 3, 4, 14 and 127 in the
OutEdge = Neg
Reduced V
Reduced V
CalDly Short
1.2 NON-EXTENDED AND EXTENDED CON-
for more information.
Low
INPUTS.
2.4.3 Output Edge Synchronization
OD
IN
OutEdge = Pos
CalDly Long
Normal V
Normal V
Rate) and the output edge
Table 10
High
OD
IN
indicates the pin
Table 10
1.1.5.3 Dou-
www.national.com
Extended
Floating
Control
Mode
DDR
DES
N/A
and
for