ADC08D1520DEV/NOPB National Semiconductor, ADC08D1520DEV/NOPB Datasheet - Page 26

• Manufacturer Part Number: ADC08D1520DEV/NOPB
• Description: BOARD DEV FOR ADC08D1520
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1520DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1520
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1520DEV

www.national.com
1.0 Functional Description
The ADC08D1520 is a versatile A/D Converter with an inno-
vative architecture permitting very high speed operation. The
controls available ease the application of the device to circuit
solutions. Optimum performance requires adherence to the
provisions discussed here and in the Applications Information
Section.
While it is generally poor practice to allow an active pin to float,
pins 4, 14, 52 and 127 of the ADC08D1520 are designed to
be left floating without jeopardy. In all discussions for pins 4,
14, and 127, whenever a function is called by allowing these
control pins to float, connecting that pin to a potential of one
half the V
ing it to float.
1.1 OVERVIEW
The ADC08D1520 uses a calibrated folding and interpolating
architecture that achieves 7.4 effective bits. The use of folding
amplifiers greatly reduces the number of comparators and
power consumption. Interpolation reduces the number of
front-end amplifiers required, minimizing the load on the input
signal and further reducing power requirements. In addition
to correcting other non-idealities, on-chip calibration reduces
the INL bow often seen with folding architectures. The result
is an extremely fast, high performance, low power converter.
The analog input signal that is within the converter's input
voltage range is digitized to eight bits at speeds of 200 MSPS
to 1.7 GSPS, typical. Differential input voltages below nega-
tive full-scale will cause the output word to consist of all
zeroes. Differential input voltages above positive full-scale
will cause the output word to consist of all ones. Either of
these conditions at either the I- or Q-channel will cause the
Out of Range (OR) output to be activated. This single OR
output indicates when the output code from one or both of the
channels is below negative full scale or above positive full
scale. When PDQ is asserted, the OR indication applies to
the I channel only.
For Non-DES Modes, each converter has a selectable output
demultiplexer which feeds two LVDS buses. If the 1:2 Demux
Mode is selected, the output data rate is reduced to half the
input sample rate on each bus. When Non-demux Mode is
selected, the output data rate on channels DI and DQ are at
the same rate as the input sample clock.
The output levels may be selected to be normal or reduced.
Using reduced levels saves power but could result in erro-
neous data capture of some or all of the bits, especially at
higher sample rates and in marginally designed systems.
1.1.1 Calibration
A calibration is performed upon power-up and can also be
invoked by the user upon command. Calibration trims the
100Ω analog input differential termination resistor and mini-
mizes full-scale error, offset error, DNL and INL, resulting in
maximizing SNR, THD, SINAD (SNDR) and ENOB. Internal
bias currents are also set during the calibration process. All
of this is true whether the calibration is performed upon power
up or is performed upon command. Running the calibration is
required for proper operation and to obtain the ADC's speci-
fied performance. In addition to the requirement to be run at
power-up, an on-command calibration must be run whenever
the sense of the FSR pin is changed. For best performance,
it is recommend that an on-command calibration be run 20
seconds or more after application of power and whenever the
operating temperature changes significantly, relative to the
specific system performance requirements. See
Command Calibration
A
supply voltage will have the same effect as allow-
for more information. Calibration can-
2.4.2.2 On-
26
not be initiated or run while the device is in the power-down
mode. See
tion between Power Down and Calibration.
In normal operation, calibration is performed just after appli-
cation of power and whenever a valid calibration command is
given, which may be accomplished one of two ways, via the
CAL pin (30) or the Calibration register (Addr: 0h, Bit 15). The
calibration command is achieved by holding the CAL pin low
for at least t
least another t
Electrical Characteristics. The time taken by the calibration
procedure is specified as t
teristics. Holding the CAL pin high upon power up will prevent
the calibration process from running until the CAL pin expe-
riences the above-mentioned t
t
CalDly (pin 127) is used to select one of two delay times that
take place from the application of power to the start of cali-
bration. This calibration delay time is dependent on the setting
of the CalDly pin and is specified as t
Electrical Characteristics. These delay values allow the pow-
er supply to come up and stabilize before calibration takes
place. If the PD pin is high upon power-up, the calibration de-
lay counter will be disabled until the PD pin is brought low.
Therefore, holding the PD pin high during power up will further
delay the start of the power-up calibration cycle. The best
setting of the CalDly pin depends upon the power-on settling
time of the power supply.
1.1.2 Acquiring the Input
In 1:2 Demux Non-DES Mode, data is acquired at the falling
edge of CLK+ (pin 18) and the digital equivalent of that data
is available at the digital outputs 13 input clock cycles later for
the DI and DQ output buses and 14 input clock cycles later
for the DId and DQd output buses. See Pipeline Delay in the
Converter Electrical Characteristics. There is an additional
internal delay called t
outputs. See the Timing Diagrams. The ADC08D1520 will
convert as long as the input clock signal is present. The fully
differential comparator design and the innovative design of
the sample-and-hold amplifier, together with self calibration,
enables a very flat SINAD/ENOB response beyond 1.5 GHz.
The ADC08D1520 output data signaling is LVDS and the out-
put format is offset binary.
1.1.3 Control Modes
Much of the user control can be accomplished with several
control pins that are provided. Examples include initiation of
the calibration cycle, power down mode and full scale range
setting. However, the ADC08D1520 also provides an Extend-
ed Control Mode whereby a serial interface is used to access
register-based control of several advanced features. The Ex-
tended Control Mode is not intended to be enabled and
disabled dynamically. Rather, the user is expected to employ
either the Non-extended Control Mode or the Extended Con-
trol Mode at all times. When the device is in the Extended
Control Mode, pin-based control of several features is re-
placed with register-based control and those pin-based con-
trols are disabled. These pins are OutV (pin 3), OutEdge/DDR
(pin 4), FSR (pin 14) and CalDly/DES (pin 127). See
EXTENDED AND EXTENDED CONTROL MODE
on the Extended Control Mode.
1.1.4 The Analog Inputs
The ADC08D1520 must be driven with a differential input sig-
nal. Operation with a single-ended signal is not recommend-
ed. It is important that the inputs either be a.c. coupled to the
CAL_H
clock cycles.
1.1.7 Power Down
CAL_L
CAL_H
clock cycles, and then holding it high for at
clock cycles, as defined in the Converter
OD
before the data is available at the
CAL
in Converter Electrical Charac-
CAL_L
for information on the interac-
clock cycles followed by
CalDly
in the Converter
for details
1.2 NON-