ADC08D1520DEV/NOPB National Semiconductor, ADC08D1520DEV/NOPB Datasheet - Page 28

• Manufacturer Part Number: ADC08D1520DEV/NOPB
• Description: BOARD DEV FOR ADC08D1520
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1520DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1520
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1520DEV

www.national.com
1.1.5.2 OutEdge and Demultiplex Control Setting
To help ease data capture in the Single Data Rate (SDR)
mode, the output data may be caused to transition on either
the positive or the negative edge of the output data clock
(DCLK). In the Non-extended Control Mode, this is selected
by OutEdge (pin 4). A logic high on the OutEdge input pin
causes the output data to transition on the rising edge of
DCLK+, while a logic low causes the output to transition on
the falling edge of DCLK+. See
nization. When in the Extended Control Mode, the OutEdge
is selected using the OED bit in the Configuration Register.
This bit has two functions. In the SDR mode, the bit functions
as OutEdge and selects the DCLK edge with which the data
transitions. In the Double Data Rate (DDR) mode, this bit se-
lects whether the device is in Non-demux or Demux Mode. In
the DDR case, the DCLK has a 0° phase relationship with the
output data, independent of the demultiplexer selection. For
1:2 Demux DDR 0° Mode, there are four, as opposed to three
cycles of CLK delay from the deassertion of DCLK_RST to
the Synchronizing Edge. See
CHRONIZATION
1.1.5.3 Double Data Rate and Single Data Rate
A choice of Single Data Rate (SDR) or Double Data Rate
(DDR) output is offered. With SDR, the output clock (DCLK)
frequency is the same as the data rate of the two output bus-
es. With DDR, the DCLK frequency is half the data rate and
data is sent to the outputs on both edges of DCLK. DDR
clocking is enabled in Non-extended Control Mode by allow-
ing pin 4 to float or by biasing it to half the supply.
1.1.5.4 Clocking Summary
The chip may be in one of four modes, depending on the Dual-
Edge Sampling (DES) selection and the demultiplex selec-
tion. For the DES selection, there are two possibilities: Non-
DES Mode and DES Mode. In Non-DES Mode, each of the
channels (I-channel and Q-channel) functions independently,
i.e. the chip is a dual 1.5 GSPS A/D converter. In DES Mode,
the I- and Q-channels are interleaved and function together
as one 3.0 GSPS A/D converter. For the demultiplex selec-
tion, there are also two possibilities: Demux Mode and Non-
Demux Mode. The I-channel has two 8-bit output busses
associated with it: DI and DId. The Q-channel also has two 8-
bit output busses associated with it: DQ and DQd. In Demux
Mode, the channel is demultiplexed by 1:2. In Non-Demux
Mode, the channel is not demultiplexed. Note that Non-De-
mux Mode is also sometimes referred to as 1:1 Demux Mode.
For example, if the I-channel was in Non-Demux Mode, the
corresponding digital output data would be available on only
respect to fall of DCLK+)
(Always sourced with
Data Outputs
DQd
DId
DQ
DI
for more information.
TABLE 2. Input Channel Samples Produced at Data Outputs in Non-Demux Mode
I-channel sampled with fall of CLK,
14 cycles earlier.
No output;
high impedance.
Q-channel sampled with fall of CLK,
13.5 cycles earlier.
No output;
high impedance.
2.4.3 Output Edge Synchro-
1.5 MULTIPLE ADC SYN-
Non-DES Sampling Mode
28
I-channel sampled with fall
of CLK,
14 cycles earlier.
No output;
high impedance.
I-channel sampled with rise
of CLK,
13.5 cycles earlier.
No output;
high impedance.
the DI bus. If the I-channel was in Demux Mode, the corre-
sponding digital output data would be available on both the
DI and DId busses, but at half the rate of Non-Demux Mode.
Given that there are two DES Mode selections (DES Mode
and Non-DES Mode) and two demultiplex selections (Demux
Mode and Non-Demux Mode), this yields a total of four pos-
sible modes: (1) Non-Demux Non-DES Mode, (2) Non-De-
mux DES Mode, (3) 1:2 Demux Non-DES Mode, and (4) 1:4
Demux DES Mode. The following is a brief explanation of the
terms and modes:
1.
2.
3.
4.
The choice of Dual Data Rate (DDR) and Single Data Rate
(SDR) will only affect the speed of the output Data Clock
(DCLK). Once the DES Modes and Demux Modes have been
chosen, the data output rate is also fixed. In the case of SDR,
the DCLK runs at the same rate as the output data; output
data may transition with either the rising or falling edge of
DCLK. In the case of DDR, the DCLK runs at half the rate of
the output data; the output data transitions on both rising and
falling edges of the DCLK.
I-Channel Selected
Non-Demux Non-DES Mode: This mode is when the chip
is in Non-Demux Mode and Non-DES Mode. The I- and
Q- channels function independently of one another. The
digital output data is available for the I-channel on DI, and
for the Q-channel on DQ.
Non-Demux DES Mode: This mode is when the chip is
in Non-Demux Mode and DES Mode. The I- and Q-
channels are interleaved and function together as one
channel. The digital output data is available on the DI and
DQ busses because although the chip is in Non-Demux
Mode, both I- and Q-channels are functioning and
passing data.
1:2 Demux Non-DES Mode: This mode is when the chip
is in Demux Mode and Non-DES Mode. The I- and Q-
channels function independently of one another. The
digital output data is available for the I-channel on DI and
DId, and for the Q-channel on DQ and DQd. This is
because each channel (I-channel and Q-channel) is
providing digital data in a demultiplexed manner.
1:4 Demux DES Mode: This mode is when the chip is in
Demux Mode and DES Mode. The I- and Q- channels
are interleaved and function together as one channel.
The digital output data is available on the DI, DId, DQ and
DQd busses because although the chip is in Demux
Mode, both I- and Q-channels are functioning and
passing data. To avoid confusion, this mode is labeled
1:4 because the analog input signal is provided on one
channel and the digital output data is provided on four
busses.
Dual-Edge Sampling (DES) Mode
Q-channel sampled with fall
of CLK,
13.5 cycles earlier.
No output;
high impedance.
Q-channel sampled with rise
of CLK,
13.5 cycles earlier.
No output;
high impedance.
Q-Channel Selected