ADC08D1520DEV/NOPB National Semiconductor, ADC08D1520DEV/NOPB Datasheet - Page 4

• Manufacturer Part Number: ADC08D1520DEV/NOPB
• Description: BOARD DEV FOR ADC08D1520
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1520DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1520
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1520DEV

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Pin Functions
Pin No.
Pin Descriptions and Equivalent Circuits
29
15
26
30
3
4
OutEdge / DDR /
OutV / SCLK
DCLK_RST /
DCLK_RST+
Symbol
SDATA
PDQ
CAL
PD
Equivalent Circuit
4
Output Voltage Amplitude and Serial Interface Clock. Tie this
pin logic high for normal differential DCLK and data
amplitude. Ground this pin for a reduced differential output
amplitude and reduced power consumption. See
LVDS
enabled, this pin functions as the SCLK input which clocks
in the serial data. See
EXTENDED CONTROL MODE
Control Mode. See
description of the serial interface.
Power Down Q-channel. A logic high on the PDQ pin puts
only the Q-channel into the Power Down Mode.
DCLK Edge Select, Double Data Rate Enable and Serial
Data Input. This input sets the output edge of DCLK+ at
which the output data transitions. See
Demultiplex Control
connected to 1/2 the supply voltage, DDR clocking is
enabled. When the Extended Control Mode is enabled, this
pin functions as the SDATA input. See
AND EXTENDED CONTROL MODE
Extended Control Mode. See
INTERFACE
DCLK Reset. When single-ended DCLK_RST is selected by
floating or setting pin 52 logic high, a positive pulse on this
pin is used to reset and synchronize the DCLK outputs of
multiple converters. See
SYNCHRONIZATION
differential DCLK_RST is selected by setting pin 52 logic low,
this pin receives the positive polarity of a differential pulse
signal used to reset and synchronize the DCLK outputs of
multiple converters.
Power Down Pins. A logic high on the PD pin puts the entire
device into the Power Down Mode.
Calibration Cycle Initiate. A minimum t
cycles logic low followed by a minimum of t
cycles high on this pin initiates the self calibration sequence.
See
2.4.2.2 On-Command Calibration
command calibration. The calibration cycle may similarly be
initiated via the CAL bit in the Calibration register (0h).
2.4.2 Calibration
Outputs. When the Extended Control Mode is
for description of the serial interface.
1.3 THE SERIAL INTERFACE
Setting. When this pin is floating or
for an overview of calibration and
1.2 NON-EXTENDED AND
for detailed description. When
Description
1.5 MULTIPLE ADC
1.3 THE SERIAL
for details on the Extended
for a description of on-
for details on the
1.2 NON-EXTENDED
CAL_L
1.1.5.2 OutEdge and
CAL_H
input clock
input clock
1.1.6 The
for