ADC08D1520DEV/NOPB National Semiconductor, ADC08D1520DEV/NOPB Datasheet - Page 29

• Manufacturer Part Number: ADC08D1520DEV/NOPB
• Description: BOARD DEV FOR ADC08D1520
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1520DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1520
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1520DEV

1.1.6 The LVDS Outputs
The Data, Out Of Range (OR+/-), and Data Clock (DCLK+/-)
outputs are LVDS. The electrical specifications of the LVDS
outputs are compatible with typical LVDS receivers available
on ASIC and FPGA chips; but they are not IEEE or ANSI
communications standards compliant due to the low +1.9V
supply used on this chip. The user is given the choice of a
lower signal amplitude via the OutV control pin or the OV
control register bit. For short LVDS lines and low noise sys-
tems, satisfactory performance may be realized with the OutV
input low, which results in lower power consumption. If the
LVDS lines are long and/or the system in which the AD-
C08D1520 is used is noisy, it may be necessary to tie the
OutV pin high.
The LVDS data outputs have a typical common mode voltage
of 800 mV when the V
higher common mode is required, this common mode voltage
can be increased to 1175 mV by tying the V
IMPORTANT NOTE: Tying the V
crease the differential LVDS output voltage by up to 40mV.
1.1.7 Power Down
The ADC08D1520 is in the active state when the Power Down
pin (PD) is low. When the PD pin is high, the device is in the
power down mode. In this mode, the data output pins (both
positive and negative) are put into a high impedance state and
the device's power consumption is reduced to a minimal level.
A logic high on the Power Down Q-channel (PDQ) pin will
power down the Q-channel and leave the I-channel active.
There is no provision to power down the I-channel indepen-
dently of the Q-channel. Upon return to normal operation, the
pipeline will contain meaningless information.
SDR or DDR Clocking
DDR Clock Phase
SDR Data transitions with rising or
falling DCLK edge
LVDS output level
Power-On Calibration Delay
Full-Scale Range
Input Offset Adjust
Feature
BG
pin is unconnected and floating. If a
BG
pin to V
Selected with pin 4
Not Selectable (0° Phase Only)
SDR Data transitions with rising edge of
DCLK+ when pin 4 is logic high and on
falling edge when low.
Normal differential data and DCLK
amplitude selected when pin 3 is logic
high and reduced amplitude selected
when low.
Short delay selected when pin 127 is logic
low and longer delay selected when high.
Normal input full-scale range selected
when pin 14 is logic high and reduced
range when low. Selected range applies
to both channels.
Not possible
BG
A
pin to V
TABLE 3. Features and Modes
Non-Extended Control Mode
will also in-
A
.
29
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
sequence is complete. However, if power is applied and PD
is already high, the device will not begin the calibration se-
quence until PD is brought low. If a manual calibration is
requested while the device is powered down, the calibration
will not take place at all. That is, the manual calibration input
is completely ignored in the power down state. Calibration will
function with the Q-channel powered down, but that channel
will not be calibrated if PDQ is high. If the Q-channel is sub-
sequently to be used, it is necessary to perform a calibration
after PDQ is brought low.
1.2 NON-EXTENDED AND EXTENDED CONTROL MODE
The ADC08D1520 may be operated in one of two control
modes: Non-extended Control Mode or Extended Control
Mode. In the simpler Non-extended Control Mode, the user
affects available configuration and control of the device
through several control pins. The Extended Control Mode
provides additional configuration and control options through
a serial interface and a set of 9 registers. Extended Control
Mode is selected by setting pin 41 to logic low. If pin 41 is
floating and pin 52 is floating or logic high, pin 14 can alter-
nately be used to enable the Extended Control Mode. The
choice of control modes is required to be a fixed selection and
is not intended to be switched dynamically while the device is
operational.
Table 3
by the control mode chosen.
shows how several of the device features are affected
Selected with nDE in the Configuration
Register (Addr-1h; bit-10).
Selected with DCP in the Configuration
Register (Addr-1h; bit-11).
Selected with OED in the Configuration
Register (Addr-1h; bit-8).
Selected with OV in the Configuration
Register (Addr-1h; bit-9).
Short delay only.
Up to 512 step adjustments over a
nominal range specified in
REGISTER
range selected for I- and Q-channels.
Selected using Full Range Registers
(Addr-3h and Bh; bit-7 through 15).
512 steps of adjustment using the Input
Offset register specified in
REGISTER DESCRIPTION
channel using Input Offset Registers
(Addr-2h and Ah; bit-7 thru 15).
Extended Control Mode
DESCRIPTION. Separate
1.4
1.4
for each
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