STEVAL-IFW001V1 STMicroelectronics, STEVAL-IFW001V1 Datasheet - Page 57

• Manufacturer Part Number: STEVAL-IFW001V1
• Description: BOARD EVAL BASED ON STR912FA
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFW001V1

• Design Resources: STEVAL-IFW001V1 Gerber Files STEVAL-IFW001V1 Schematic STEVAL-IFW001V1 Bill of Material
• Main Purpose: Interface, Ethernet
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: E-STE101P, STR912FAW44
• Primary Attributes: Dual Ethernet Transceivers for Full Duplex Communication
• Secondary Attributes: Up to 32 MII Addresses, UART, I2C, SPI, with RJ45 Connectors
• Silicon Manufacturer: ST Micro
• Core Architecture: ARM
• Core Sub-architecture: ARM9
• Silicon Core Number: STR9
• Silicon Family Name: STR91x
• For Use With: 497-8263 - BOARD EXTENSION STEVAL-IFW001V1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8262

STR91xFAxxx
Figure 9.
0xFC01.0000
0xFC00.0000
0x7C00.0000
0x6C00.0000
0x5C00.0000
0x4C00.0000
0x3C00.0000
0x2C00.0000
0xFFFF.FFFF
0xFFFF.F000
0x8000.0000
0x7800.0000
0x7400.0000
0x7000.0000
0x6800.0000
0x6400.0000
0x6000.0000
0x5800.0000
0x5400.0000
0x5000.0000
0x4800.0000
0x4400.0000
0x4000.0000
0x3800.0000
0x3400.0000
0x3000.0000
0x2800.0000
0x2400.0000
0x2000.0000
0x0800.0000
0x0400.0000
0x0000.0000
STR91xFA memory map
TOTAL 4 GB CPU
MEMORY SPACE
Ext. MEM, CS0
Ext. MEM, CS1
Ext. MEM, CS2
Ext. MEM, CS3
Ext. MEM, CS0
Ext. MEM, CS1
Ext. MEM, CS2
Ext. MEM, CS3
SRAM, D-TCM
FLASH, I-TCM
RESERVED
RESERVED
SRAM, AHB
SRAM, AHB
RESERVED
8-CH DMA
8-CH DMA
ENET
ENET
APB1
APB0
APB1
APB0
VIC0
VIC1
USB
USB
EMI
EMI
FMI
FMI
4 KB
64 KB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
64 MB
Using 64 KB or 96
KB
Using 288 KB, 544 KB,
1.1 MB or 2.1 MB
BUFFERED
BUFFERED
BUFFERED
BUFFERED
BUFFERED
BUFFERED
BUFFERED
NON-
NON-
NON-
NON-
AHB
AHB
AHB
AHB
AHB
AHB
AHB
Doc ID 13495 Rev 6
BUFFERED ACCESS
PERIPHERAL BUS,
NON- BUFFERED
PERIPHERAL BUS,
0x0000.0000
ACCESS
Order of the two Flash memories is user defined.
1024KB or 2028KB
FLASH (BANK 1),
DEFAULT ORDER
32KB or 128KB
256KB, 512KB,
SECONDARY
MAIN FLASH
APB1+0x0000.A000
APB0+0x0000.A000
(BANK 0),
APB1+0x0000.D000
APB1+0x0000.C000
APB1+0x0000.B000
APB0+0x0000.D000
APB0+0x0000.C000
APB0+0x0000.B000
APB1+0x03FF.FFFF
APB1+0x0000.E000
APB1+0x0000.9000
APB1+0x0000.8000
APB1+0x0000.7000
APB1+0x0000.6000
APB1+0x0000.5000
APB1+0x0000.4000
APB1+0x0000.3000
APB1+0x0000.2000
APB1+0x0000.1000
APB1+0x0000.0000
APB0+0x03FF.FFFF
APB0+0x0001.0000
APB0+0x0000.F000
APB0+0x0000.E000
APB0+0x0000.9000
APB0+0x0000.8000
APB0+0x0000.7000
APB0+0x0000.6000
APB0+0x0000.5000
APB0+0x0000.4000
APB0+0x0000.3000
APB0+0x0000.2000
APB0+0x0000.1000
APB0+0x0000.0000
APB BASE +
OFFSET
1024KB or 2048KB
OPTIONAL ORDER
FLASH (BANK 1),
PERIPHERAL BUS
MEMORY SPACE
WAKE-UP UNIT
GPIO PORT P9
GPIO PORT P8
GPIO PORT P7
GPIO PORT P6
GPIO PORT P5
GPIO PORT P4
GPIO PORT P3
GPIO PORT P2
GPIO PORT P1
GPIO PORT P0
256KB, 512KB,
32KB or 128KB
APB1 CONFIG
APB0 CONFIG
SECONDARY
MAIN FLASH
WATCHDOG
RESERVED
RESERVED
(BANK 0),
UART2
UART1
UART0
SSP1
SSP0
TIM3
TIM2
TIM1
TIM0
I2C1
I2C0
ADC
CAN
SCU
RTC
IMC
Memory mapping
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
APB1,
AHB-
to-APB
Bridge
APB0,
AHB-
to-APB
Bridge
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