STEVAL-IFW001V1 STMicroelectronics, STEVAL-IFW001V1 Datasheet - Page 37

• Manufacturer Part Number: STEVAL-IFW001V1
• Description: BOARD EVAL BASED ON STR912FA
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFW001V1

• Design Resources: STEVAL-IFW001V1 Gerber Files STEVAL-IFW001V1 Schematic STEVAL-IFW001V1 Bill of Material
• Main Purpose: Interface, Ethernet
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: E-STE101P, STR912FAW44
• Primary Attributes: Dual Ethernet Transceivers for Full Duplex Communication
• Secondary Attributes: Up to 32 MII Addresses, UART, I2C, SPI, with RJ45 Connectors
• Silicon Manufacturer: ST Micro
• Core Architecture: ARM
• Core Sub-architecture: ARM9
• Silicon Core Number: STR9
• Silicon Family Name: STR91x
• For Use With: 497-8263 - BOARD EXTENSION STEVAL-IFW001V1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8262

STR91xFAxxx
3.26
Three-phase induction motor controller (IMC)
The STR91xFA provides an integrated controller for variable speed motor control
applications.
Six PWM outputs are generated on high current drive pins P6.0 to P6.5 for controlling a
three-phase AC induction motor drive circuit assembly. Rotor speed feedback is provided by
capturing a tachometer input signal on pin P6.6, and an asynchronous hardware emergency
stop input is available on pin P6.7 to stop the motor immediately if needed, independently of
firmware.
The IMC unit has the following features:
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Three PWM outputs generated using a 10 or 16-bit PWM counter, one for each phase
U, V, W. Complimentary PWM outputs are also generated for each phase.
Choice of classic or zero-centered PWM generation modes
10 or 16-bit PWM counter clock is supplied through a programmable 8-bit prescaler of
the APB clock.
Programmable 6 or 10-bit dead-time generator to add delay to each of the three
complimentary PWM outputs
8-bit repetition counter
Automatic rotor speed measurement with 16-bit resolution. Schmitt trigger tachometer
input with programmable edge detection
Hardware asynchronous emergency stop input
A dedicated interrupt to CPU with eight flags
Enhanced Motor stop output polarity configuration
Double update option when PWM counter reaches the max and min values in Zero-
centered mode
Locking feature to prevent some control register bits from being advertently modified
Trigger output to start an ADC conversion
Doc ID 13495 Rev 6
Functional overview
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