STEVAL-IFW001V1 STMicroelectronics, STEVAL-IFW001V1 Datasheet - Page 31

• Manufacturer Part Number: STEVAL-IFW001V1
• Description: BOARD EVAL BASED ON STR912FA
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFW001V1

• Design Resources: STEVAL-IFW001V1 Gerber Files STEVAL-IFW001V1 Schematic STEVAL-IFW001V1 Bill of Material
• Main Purpose: Interface, Ethernet
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: E-STE101P, STR912FAW44
• Primary Attributes: Dual Ethernet Transceivers for Full Duplex Communication
• Secondary Attributes: Up to 32 MII Addresses, UART, I2C, SPI, with RJ45 Connectors
• Silicon Manufacturer: ST Micro
• Core Architecture: ARM
• Core Sub-architecture: ARM9
• Silicon Core Number: STR9
• Silicon Family Name: STR91x
• For Use With: 497-8263 - BOARD EXTENSION STEVAL-IFW001V1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8262

STR91xFAxxx
3.18
The STR91xFA MAC includes the following features:
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A 32-bit burst DMA channel residing on the AHB is dedicated to the Ethernet MAC for high-
speed data transfers, side-stepping the CPU for minimal CPU impact during transfers. This
DMA channel includes the following features:
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USB 2.0 slave device interface with DMA
The STR91xFA provides a USB slave controller that implements both the OSI Physical and
Data Link layers for direct bus connection by an external USB host on pins USBDP and
USBPN. The USB interface detects token packets, handles data transmission and
reception, and processes handshake packets as required by the USB 2.0 standard.
The USB slave interface includes the following features:
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Supports 10 and 100 Mbps rates
Tagged MAC frame support (VLAN support)
Half duplex (CSMA/CD) and full duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and group
addresses)
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. Transmit FIFO depth is 4 words
(32 bits each), and the receive FIFO is 16 words deep.
Direct SRAM to MAC transfers of transmit frames with the related status, by descriptor
chain
Direct MAC to SRAM transfers of receive frames with the related status, by descriptor
chain
Open and Closed descriptor chain management
Supports USB low and full-speed transfers (12 Mbps), certified to comply with the USB
2.0 specification
Supports isochronous, bulk, control, and interrupt endpoints
Configurable number of endpoints allowing a mixture of up to 20 single-buffered
monodirectional endpoints or up to 10 double-buffered bidirectional endpoints
Dedicated, dual-port 2 Kbyte USB Packet Buffer SRAM. One port of the SRAM is
connected by a Packet Buffer Interface (PBI) on the USB side, and the CPU connects
to the other SRAM port.
CRC generation and checking
NRZI encoding-decoding and bit stuffing
USB suspend resume operations
Doc ID 13495 Rev 6
Functional overview
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