STEVAL-IFW001V1 STMicroelectronics, STEVAL-IFW001V1 Datasheet - Page 21

• Manufacturer Part Number: STEVAL-IFW001V1
• Description: BOARD EVAL BASED ON STR912FA
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFW001V1

• Design Resources: STEVAL-IFW001V1 Gerber Files STEVAL-IFW001V1 Schematic STEVAL-IFW001V1 Bill of Material
• Main Purpose: Interface, Ethernet
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: E-STE101P, STR912FAW44
• Primary Attributes: Dual Ethernet Transceivers for Full Duplex Communication
• Secondary Attributes: Up to 32 MII Addresses, UART, I2C, SPI, with RJ45 Connectors
• Silicon Manufacturer: ST Micro
• Core Architecture: ARM
• Core Sub-architecture: ARM9
• Silicon Core Number: STR9
• Silicon Family Name: STR91x
• For Use With: 497-8263 - BOARD EXTENSION STEVAL-IFW001V1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8262

STR91xFAxxx
3.10.2
3.10.3
3.10.4
As an option, there are a number of peripherals that do not have to receive a clock sourced
from the CCU. The USB interface can receive an external clock on pin P2.7, TIM timers
TIM0/ TIM1 can receive an external clock on pin P2.4, and timers TIM2/TIM3 on pin P2.5.
Figure 2.
Reference clock (RCLK)
The main clock (f
(RCLK) for the ARM core and all the peripherals. The RCLK provides the divided clock for
the ARM core, and feeds the dividers for the AHB, APB, External Memory Interface, and
FMI units.
AHB clock (HCLK)
The RCLK can be divided by 1, 2 or 4 to generate the AHB clock. The AHB clock is the bus
clock for the AHB bus and all bus transfers are synchronized to this clock. The maximum
HCLK frequency is 96 MHz.
APB clock (PCLK)
The RCLK can be divided by 1, 2, 4 or 8 to generate the APB clock. The APB clock is the
bus clock for the APB bus and all bus transfers are synchronized to this clock. Many of the
peripherals that are connected to the AHB bus also use the PCLK as the source for external
bus data transfers. The maximum PCLK frequency is 48 MHz.
EXTCLK_T2T3
EXTCLK_T0T1
USB_CLK48M
MII_PHYCLK
X1_CPU
X1_RTC
X1_CPU
X2_RTC
JRTCLK
4-25MHz
Clock control
32.768 kHz
48MHz
25MHz
MSTR
Main
OSC
RTC
OSC
) can be divided to operate at a slower frequency reference clock
External clock
Timer 2 & 3
External clock
Timer 0 & 1
f
OSC
32.768 kHz
Doc ID 13495 Rev 6
f
RTC
RTCSEL
PHYSEL
PLL
f
PLL
Master CLK
f
MSTR
(1,2,4,8,16,1024)
1/2
1/2
RCLK
DIV
USBCLK to USB
BRCLK to SSPs and UARTs
Functional overview
RCLK
1/2
1/2
AHB DIV
APB DIV)
(1,2,4)
(1,2,4,8)
CPUCLK
FMICLK
EMI_BCLK
21/102
PCLK
HCLK