DLP-2232M-G DLP Design Inc, DLP-2232M-G Datasheet - Page 6

• Manufacturer Part Number: DLP-2232M-G
• Description: MODULE USB ADAPTER FOR FT2232D
• Manufacturer: DLP Design Inc

Specifications of DLP-2232M-G

• Main Purpose: Interface, USB 2.0 to UART (RS232) Bridge
• Embedded: No
• Utilized Ic / Part: FT2232D
• Primary Attributes: Full Speed USB to High-Speed UART
• Secondary Attributes: Royalty-Free Drivers, 2K EEPROM
• Interface Type: USB
• Data Bus Width: 8 bit
• Operating Supply Voltage: 4.35 V to 5.25 V
• Product: Interface Modules
• For Use With/related Products: FT2232D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 813-1000

• CPU-Style FIFO Interface
The CPU style FIFO interface is essentially the same function as the classic FT245
interface, however the bus signals have been redefined to make them easier to interface to
a CPU bus.
• Multi-Protocol Synchronous Serial Engine Interface (M.P.S.S.E.)
The Multi-Protocol Synchronous Serial Engine (MPSSE) interface is a new option
designed to interface efficiently with synchronous serial protocols such as JTAG and SPI
Bus. It is very flexible in that it can be configured for different industry standards, or
proprietary bus protocols. For instance, it is possible to connect one of the DLP-2232M-
G’s channels to an SRAM configurable FPGA as supplied by vendors such as Altera and
Xilinx. The FPGA device would normally be un-configured (i.e. have no defined
function) at power-up. Application software on the PC could use the MPSSE to
download configuration data to the FPGA over USB. This data would define the
hardware’s function and then, after the FPGA device is configured, the DLP-2232M-G
can switch back into FIFO interface mode to allow the programmed FPGA device to
communicate with the PC over USB. The other DLP-2232M-G channel would also be
available for other devices.
This approach would allow a customer to create a “generic” USB peripheral; who’s
hardware function can be defined under control of the application software. The FPGA
based hardware could be easily upgraded or totally changed simply by changing the
FPGA configuration data file. (See the FTDI MORPH-IC or DLP-Design DLP-2232PB
and DLP-2232SY development modules for practical examples)
• MCU Host Bus Emulation
This new mode combines the ‘A’ and ‘B’ bus interface to make the DLP-2232M-G
interface emulate a standard 8048 / 8051 style MCU bus. This allows peripheral devices
for these MCU families to be directly attached to the DLP-2232M-G with IO being
performed over USB with the help of MPSSE interface technology.
• Fast Opto-Isolated Serial Interface
A new proprietary FTDI protocol is designed to allow galvanically isolated devices to
communicate synchronously with the DLP-2232M-G using just 4 wires (two dual opto-
isolators). The peripheral circuitry controls the data transfer rate in both directions,
whilst maintaining full data integrity. Maximum USB full speed data rates can be
achieved. Both ‘A’ and ‘B’ channels can communicate over the same 4-wire interface if
desired.
Rev 1.6 (May 2009)
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DLP-2232M-G DLP Design, Inc.