MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 7

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5:
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
58, 59, 61, 62, 64, 70, 179, 180,
182, 183, 185, 186, 191, 199
55 (1GB), 71, 192
Pin Numbers
(512MB, 1GB)
73, 75, 194
188, 189
198
196
Pin Descriptions
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 6 for more information
53
(512MB, 1GB)
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
RAS#, CAS#,
CK0, CK0#
BA2
BA0, BA1,
Symbol
(256MB)
A0–A12
A0-A13
ODT0
CKE0
WE#
S0#
(1GB)
Type
Input
Input
Input
Input
Input
Input
Input
On-Die termination: ODT (registered HIGH) enables termination
resistance internal to the DDR2 SDRAM. When enabled, ODT is
only applied to each of the following pins: DQ, DQS, DQS#,
RDQS, RDQS#, CB, and DM. The ODT input will be ignored if
disabled via the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered
LOW) deactivates clocking circuitry on the DDR2 SDRAM. The
specific circuitry that is enabled/disabled is dependent on the
DDR2 SDRAM configuration and operating mode. CKE LOW
provides PRECHARGE power-down and SELF REFRESH operations
(all device banks idle), or ACTIVE power-down (row ACTIVE in
any device bank). CKE is synchronous for power-down entry,
power-down exit, output disable, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit. Input buffers
(excluding CK, CK#, CKE, and ODT) are disabled during power-
down. Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_18 input but will detect a LVCMOS LOW
level once V
become stable during the power on and initialization sequence,
it must be maintained for proper operation of the CKE receiver.
For proper SELF REFRESH operation V
this input.
Chip select: S# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when S#
is registered HIGH. S# provides for external rank selection on
systems with multiple ranks. S# is considered part of the
command code.
Command inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Bank address inputs: BA0–BA1/BA2 define to which device bank
an ACTIVE, READ, WRITE, or PRECHARGE command is being
applied. BA0–BA1 define which mode register including MR,
EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE
command.
Address inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for Read/
WRITE commands, to select one location out of the memory array
in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
device bank (A10 LOW, device bank selected by BA0–BA1/BA2) or
all device banks (A10 HIGH). The address inputs also provide the
op-code during a LOAD MODE command.
7
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
is applied during first power-up. After V
Pin Assignments and Descriptions
Description
©2004, 2005 Micron Technology, Inc. All rights reserved.
REF
must be maintained to
REF
has