MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 42

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Presence-Detect
SPD Clock and Data Conventions
SPD Start Condition
SPD Stop Condition
SPD Acknowledge
Figure 12:
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
Data Validity
Data states on the SDA line can change only during SCL LOW. SDA state changes during
SCL HIGH are reserved for indicating start and stop conditions (Figure 12, and Figure 13
on page 43).
All commands are preceded by the start condition, which is a HIGH-to-LOW transition
of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any command until this condition
has been met.
All communications are terminated by a stop condition, which is a LOW-to-HIGH tran-
sition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device
into standby power mode.
Acknowledge is a software convention used to indicate successful data transfers. The
transmitting device, either master or slave, will release the bus after transmitting 8 bits.
During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge
that it received the 8 bits of data (Figure 14 on page 43).
The SPD device will always respond with an acknowledge after recognition of a start
condition and its slave address. If both the device and a WRITE operation have been
selected, the SPD device will respond with an acknowledge after the receipt of each sub-
sequent 8-bit word. In the read mode the SPD device will transmit 8 bits of data, release
the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and
no stop condition is generated by the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will terminate further data transmissions and
await the stop condition to return to standby power mode.
SDA
SCL
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
DATA STABLE
DATA
CHANGE
42
DATA STABLE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Serial Presence-Detect
©2004, 2005 Micron Technology, Inc. All rights reserved.