MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 41

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 22:
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
Parameter
Output Enable to any Y/Y#
Output Enable to any Y/Y#
Cycle to Cycle Jitter
Static Phase Offset
Dynamc Phase Offset
Output Clock Skew
Period Jitter
Half-Period Jitter
Input Clock Slew Rate
Output Clock Slew Rate
Output Differential-Pair Cross-Voltage
SSC Modulation Frequency
SSC Clock Input Frequency Deviation
PLL Loop Bandwidth (-3dB from unity gain)
PLL Clock Driver Timing Requirements and Switching Characteristics
Note: 1
Notes: 1. Timing and switching specifications for the PLL listed above are critical for proper opera-
2. Static phase offset does not include Jitter.
3. Period Jitter and Half-Period Jitter specifications are separate specifications that must be
4. Design target is 60ps, unless it is unachievable.
5. V
6. The output slew rate is determined from the IBIS model:
CU878
tion of the DDR2 SDRAM Registered DIMMs. These are meant to be a subset of the param-
eters for the specific device used on the module. Detailed information for this PLL is
available in JEDEC Standard JESD82.
met independently of each other.
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
OX
GND
V
DD
specified at the DRAM clock input, or the test load.
Symbol
t
t
V
V
t
JIT
t
t
JIT
t
∅
t
V
JIT
t
t
CK
CK
SK
DIS
t
LS
EN
LS
∅
OX
dyn
HPER
PER
R = 60
R = 60
CC
O
O
I
41
V
DD
V
Q/2 - 0.1
Min
-40
-50
-50
-40
-75
1.0
1.5
0.0
2.0
2
DD
30
–
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
V
0°C ≤ T
DD
= +1.8V ±0.1V
Nominal
PLL and Register Specifications
OPR
2.5
2.5
–
–
–
0
0
–
–
–
–
–
–
–
≤ +55°C
V
©2004, 2005 Micron Technology, Inc. All rights reserved.
DD
Q/2 + 0.1
-0.50
Max
40
50
50
40
40
75
33
8
8
4
3
–
Units
MHz
V/ns
V/ns
kHZ
ns
ns
ps
ps
ps
ps
ps
ps
%
V
Notes
3, 4
2
2
3
6
5