MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 21

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DQS# Enable/Disable
RDQS Enable/Disable
Output Enable/Disable
On Die Termination (ODT)
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
The DQS# enable function is defined by bit E10. When enabled (bit E10 = 0), DQS# is the
complement of the differential data strobe pair DQS/DQS#. When disabled (bit E10 = 1),
DQS is used in a single-ended mode and the DQS# pin is disabled. This function is also
used to enable/disable RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled
(E10 = 0), then both DQS# and RDQS# will be enabled. RDQS/RDQS# is supported only
on RDIMMs using x8 DDR2 SDRAM devices.
RDQS/RDQS# is supported only on RDIMMs using x8 DDR2 SDRAM devices. The RDQS
enable function is defined by bit E11 as shown in Figure 7 on page 20. When enabled
(E11 = 1), RDQS is identical in function and timing to data strobe DQS during a READ.
During a WRITE operation, RDQS is ignored by the DDR2 SDRAM device.
The OUTPUT enable function is defined by bit E12 as shown in Figure 7. When enabled
(E12 = 0), all outputs (DQs, DQS, DQS#, RDQS, RDQS#) function normally. When dis-
abled (E12 = 1), all DDR2 SDRAM device outputs (DQs, DQS, DQS#, RDQS, RDQS#) are
disabled removing output buffer current. The OUTPUT disable feature is intended to be
used during I
ODT effective resistance R
Figure 7. The ODT feature is designed to improve signal integrity of the memory channel
by allowing the DDR2 SDRAM device controller to independently turn on/off ODT for
any or all devices. R
apply to each DQ, DQS/DQS#, RDQS/RDQS#, and DM signals. Additionally, the -667
speed modules offer a third option of 50Ω. Reserved states should not be used, as
unknown operation or incompatibility with future versions may result.
The ODT control pin is used to determine when R
ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input
pin are only used during active, active power-down (both fast-exit and slow-exit modes),
and precharge power-down modes of operation. If SELF REFRESH operation is used,
R
SDRAM device. During power-up and initialization of the DDR2 SDRAM device, ODT
should be disabled until the EMR command is issued to enable the ODT feature, at
which point the ODT pin will determine the R
or 1Gb DDR2 SDRAM discrete data sheet for ODT timing diagrams.
TT
(
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
EFF
) should always be disabled and the ODT input pin is disabled by the DDR2
DD
characterization of read current.
TT
effective resistance values of 75Ω and 150Ω are selectable and
TT
(
EFF
21
) is defined by bits E2 and E6 of the EMR as shown in
Micron Technology, Inc., reserves the right to change products or specifications without notice.
TT
(
EFF
TT
(
) value. Refer to the 256Mb, 512Mb,
EFF
) is turned on and off, assuming
©2004, 2005 Micron Technology, Inc. All rights reserved.
DQS# Enable/Disable