MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 29

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 15:
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
Parameter/Condition
Operating one bank active-precharge current;
(I
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Operating one bank active-read-precharge current; I
CL = CL(I
=
inputs are SWITCHING; Data pattern is same as I
Precharge power-down current; All device banks idle;
is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING.
Precharge quiet standby current; All device banks idle;
is HIGH, S# is HIGH; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING.
Precharge standby current; All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are SWITCHING; Data
bus inputs are SWITCHING.
Active power-down current; All device banks open;
t
STABLE; Data bus inputs are FLOATING.
Active standby current; All device banks open;
MAX (I
Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
Operating burst write current; All device banks open, Continuous burst
writes; BL = 4, CL = CL (I
t
inputs are SWITCHING; Data bus inputs are SWITCHING.
Operating burst read current; All device banks open, Continuous burst
reads, I
MAX (I
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Burst refresh current;
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are FLOATING.
Operating bank interleave read current; All device banks interleaving
reads, I
(I
HIGH between valid commands; Address bus inputs are STABLE during
DESELECTs; Data bus inputs are SWITCHING; See “I
page 28 for details.
CK (I
RP =
DD
DD
t
RCD (I
),
),
DD
t
t
t
RAS =
RP (I
RC =
DD
DD
OUT
OUT
); CKE is LOW; Other control and address bus inputs are
DD
DD
),
),
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus
t
= 0mA; BL = 4, CL = CL (I
t
t
RP =
RP =
RC(I
t
RAS MIN (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus
I
Values shown for DDR2 SDRAM components only
DD
DD
t
t
RP(I
RP (I
Specifications and Conditions – 256MB
),
t
t
CK =
RRD =
DD
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid commands;
); CKE is HIGH, S# is HIGH between valid commands;
t
CK =
t
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands;
CK (I
t
RRD(I
t
DD
CK (I
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
),
DD
DD
t
DD
t
DD
RC =
CK =
),
), AL =
), AL = 0;
); Refresh command at every
t
RCD =
t
RC (I
t
CK (I
t
RCD (I
t
DD
RCD(I
DD
t
DD
CK =
),
),
t
CK =
t
4W.
RAS =
DD
DD
t
t
DD
RAS =
CK =
t
CK =
t
)-1 ×
7 Conditions” on
CK (I
); CKE is HIGH, S# is
t
CK =
t
CK(I
t
t
t
OUT
RAS MIN (I
CK (I
CK =
t
t
t
DD
t
CK (I
CK =
RAS MAX (I
CK (I
29
DD
),
= 0mA; BL = 4,
DD
),
t
t
DD
RAS =
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
DD
t
CK (I
CK (I
t
),
RAS =
); CKE is
);
t
t
RC =
RFC (I
t
DD
DD
CK =
DD
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
RAS
),
); CKE
); CKE
t
RAS
t
),
t
RCD
DD
RC
t
CK
I
)
DD
Symbol
I
I
I
I
I
I
I
DD
Specifications and Conditions
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
1,710
1,620
1,620
2,340
-667
810
900
360
360
270
450
45
54
45
©2004, 2005 Micron Technology, Inc. All rights reserved.
1,440
1,350
1,530
2,160
-53E
720
810
315
315
225
360
45
54
45
1,125
1,035
1,485
2,070
-40E
675
765
225
270
180
270
45
54
45
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA