MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 12

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Presence-Detect Operation
Initialization
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
10. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e., to
11. Issue a LOAD MODE command to the EMR to enable OCD default by setting Bits E7,
12. Issue a LOAD MODE command to the EMR to enable OCD exit by setting Bits E7, E8,
1. Apply power; if CKE is maintained below 20 percent of V
2. The voltage difference between any V
3. Wait a minimum of 400ns, then issue a PRECHARGE ALL command.
4. Issue a LOAD MODE command to the EMR(2) register. (To issue an EMR(2) com-
5. Issue a LOAD MODE command to the EMR(3) register. (To issue an EMR(3) com-
6. Issue a LOAD MODE command to the EMR register to enable DLL. To issue a DLL
7. Issue a LOAD MODE command for DLL reset. 200 cycles of clock input is required to
8. Issue PRECHARGE ALL command.
9. Issue two or more REFRESH commands.
DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of stor-
age are available for use by the customer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device occur via a standard I
the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide
eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the
module, permanently disabling hardware write protect.
The following sequence is required for power-up and initialization and is shown in
Figure 4 on page 13.
The DDR2 SDRAM device is now intialized and ready for normal operation 200 clocks
after DLL reset in step 7.
abled. To guarantee R
applied to the ODT pin (all other inputs may be undefined). The time from when V
first starts to power up to the completion of V
At least one of the following two sets of conditions (A or B) must be met:
of 200µs after stable power and clock (CK, CK#), apply NOP or DESELECT commands
and take CKE HIGH.
mand, provide LOW to BA0 and BA2, provide HIGH to BA1.)
mand, provide HIGH to BA0 and BA1, provide LOW to BA2.)
ENABLE command, provide LOW to BA1, BA2, and A0, provide HIGH to BA0. Bits E7,
E8, and E9 must all be set to 0.
lock the DLL. (To issue a DLL reset, provide HIGH to A8 and provide LOW to BA2, BA1
and BA0.) CKE must be HIGH the entire time.
program operating parameters without resetting the DLL).
E8, and E9 to 1 and set all other desired parameters.
and E9 to 0 and set all other desired parameters.
A. V
B. Apply V
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
• V
• V
• Apply V
• Apply V
DD
, V
TT
REF
DD
is limited to 0.95V MAX
DD
tracks V
L and V
DD
DD
before or at the same time as V
L before or at the same time as V
Q before or at the same time as V
DD
DD
TT
Q/2
Q are driven from a single power converter output
(ODT resistance) is off, V
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
supply can not exceed 0.3V. For a minimum
Serial Presence-Detect Operation
DD
DD
Q must be equal to or less than 20ms.
L.
REF
DD
TT
Q
and V
must be valid and LOW must be
DD
©2004, 2005 Micron Technology, Inc. All rights reserved.
REF
Q, outputs remain dis-
2
C bus using
DD