MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 22

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Off-Chip Driver (OCD) Impedance Calibration
Posted CAS Additive Latency
Figure 8:
Figure 9:
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
COMMAND
DQS, DQS#
CK#
DQ
CK
COMMAND
DQS, DQS#
ACTIVE n
CK#
DQ
CK
T0
READ Latency
Write Latency
ACTIVE n
T0
Notes: 1. BL = 4. Shown with nominal
Notes: 1. BL = 4.
READ n
T1
The OCD function is not supported and must be set to the default state. See “Initializa-
tion” on page 12, to properly set OCD defaults.
Posted CAS additive latency (AL) is supported to make the command and data bus effi-
cient for sustainable bandwidths in DDR2 SDRAM device. Bits E3–E5 define the value of
AL as shown in Figure 7 on page 20. Bits E3–E5 allow the user to program the DDR2
SDRAM device with an AL of 0, 1, 2, 3, or 4 clocks. Reserved states should not be used as
unknown operation or incompatibility with future versions may result.
In this operation, the DDR2 SDRAM device allows a READ or WRITE command to be
issued prior to
tion using this feature would set AL =
mand is held for the time of the additive latency (AL) before it is issued internally to the
DDR2 SDRAM device. RL is controlled by the sum of the posted AL and CL; RL = AL + CL.
Write latency (WL) is equal to RL minus one clock; WL = AL + CL - 1 ×
RL is shown in Figure 8. An example of WL is shown in Figure 9.
t RCD (MIN)
2. CL = 3
2. CL = 3
WRITE n
T1
AL = 2
RL = AL + CL = 5.
AL = 2
WL = AL + CL -1 = 4.
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
t
RCD (MIN)
AL = 2
NOP
T2
AL = 2
NOP
t
T2
RCD (MIN) with the requirement that AL ≤
NOP
T3
WL = AL + CL - 1 = 4
RL = 5
NOP
T3
Off-Chip Driver (OCD) Impedance Calibration
22
t
AC,
NOP
T4
t
DQSCK, and
t
CL - 1 = 2
CL = 3
RCD (MIN) - 1 ×
NOP
T4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
T5
t
DQSQ.
NOP
T5
D
n
in
TRANSITIONING DATA
t
CK. The READ or WRITE com-
NOP
n + 1
T6
D
in
t
RCD(MIN). A typical applica-
©2004, 2005 Micron Technology, Inc. All rights reserved.
D
OUT
n
NOP
n + 2
T6
D
in
D
n + 1
OUT
NOP
n + 3
t
T7
D
CK. An example of
in
D
n + 2
OUT
DON’T CARE
NOP
T7
D
n + 3
OUT
NOP
T8