MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 44

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 23:
Table 24:
Figure 15:
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
Select Code
Memory area select code (two arrays)
Protection register select code
Mode
Current address read
Random address read
Sequential read
Byte write
Page write
SDA OUT
SDA IN
SCL
EEPROM Device Select Code
The most significant bit (b7) is sent first
EEPROM Operating Modes
SPD EEPROM Timing Diagram
t SU:STA
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
RW Bit
1
0
1
1
0
0
t F
t HD:STA
t LOW
t AA
V
V
V
V
IH
IH
IH
IH
WC
V
V
or V
or V
or V
or V
IL
IL
b7
IL
IL
IL
IL
1
0
t HIGH
t HD:DAT
Device Type Identifier
Bytes
≤ 16
44
≥ 1
1
1
1
1
b6
0
1
t DH
Initial Sequence
START, Device select, RW = ‘1’
START, Device select, RW = ‘0’, Address
reSTART, Device select, RW = ‘1’
Similar to current or random address read
START, Device select, RW = ‘0’
START, Device select, RW = ‘0’
t R
Micron Technology, Inc., reserves the right to change products or specifications without notice.
b5
1
1
t SU:DAT
b4
0
0
SA2
SA2
b3
Serial Presence-Detect
©2004, 2005 Micron Technology, Inc. All rights reserved.
Chip Enable
t SU:STO
SA1
SA1
b2
t BUF
UNDEFINED
SA0
SA0
b1
RW
RW
RW
b0