IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet - Page 57

• Manufacturer Part Number: IDT72P51777L7-5BBI
• Description: IC FLOW CTRL 40BIT 376-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51777L7-5BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51777L7-5BBI

INPUT INTERFACE
data clocking. No device configuration is required. For reference XGMII uses
center aligned clocking.
or Double Data Rate (DDR) data transfers.
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
The input port will support either Edge Aligned data clocking or Center Aligned
The input interface will support either Single Data Rate (SDR) data transfers
TABLE 15 — INTERFACE DATA RATES
Input Interface
DDR
DDR
SDR
SDR
ERCLK
(PLL-ON)
ERCLK
(PLL-ON)
data
Data
Figure 34. DDR Source Synchronous Center Aligned Clocking
ta_max
DDR Cycle Time
Output Interface
Figure 35. SDR Edge Aligned Clocking
DDR
DDR
SDR
SDR
tsu_min
SDR Cycle Time
D0
57
OUTPUT INTERFACE
Data Rate (DDR) operation and Edge Aligned data clock for Single Data Rate
(SDR) operation. The output interface will support either Single Data Rate
(SDR) data transfers or Double Data Rate (DDR) data transfers.
The output interface will provide a Centered Aligned data clock for Double
Note, the sum of (ta max + tsu min) must be less than the cycle time.
Supported Data Transfer Rate
Combination
Yes
Yes
Yes
Yes
D1
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009