IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet - Page 13

• Manufacturer Part Number: IDT72P51777L7-5BBI
• Description: IC FLOW CTRL 40BIT 376-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51777L7-5BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51777L7-5BBI

PIN DESCRIPTIONS (CONTINUED)
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
RCLK (Cont'd) Read Clock
(J22)
RCS
(J21)
RDADD[7:0]
(RDADD7-V20 Bus
RDADD6-V21
RDADD5-V22
RDADD4-U20
RDADD3-U21
RDADD2-U22
RDADD1-T20
RDADD0-T21)
REN
(J20)
SCLK
(K3)
SENI
(K1)
SENO
(K2)
SI
(L2)
SO
(L3)
TCK
(B10)
Symbol &
Pin No.
Read Chip
Select
Read Address
Read Enable
Serial Clock
Serial Input
Enable
Serial Output
Enable
Serial In
Serial Out
JTAG Clock
Name
I/O TYPE
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
EF outputs are all synchronized to RCLK. During device expansion the EXO and EXI signals are based
on RCLK. RCLK must be continuous and free-running.
The RCS signal in concert with REN signal provides control to enable data on to the output read data
bus. During a Master Reset cycle the RCS it is don’t care signal.
For the 128Q device the RDADD bus is 8 bits. The RDADD bus is a dual purpose address bus. The first
function of RDADD is to select a Queue to be read from. The least significant 5 bits of the bus, RDADD[4:0]are
used to address 1 of 128 possible queues within a multi-queue device. The most significant 3 bits,
RDADD[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion
mode. These 3 MSB’s will address a device with the matching ID code. (See ID[2:0] description for more
detail on matching ID code. The second function of the RDADD bus is to select the quadrant of queues
to be loaded on to the PAEn bus during strobed flag mode. The least significant 4 bits, RDADD[3:0] are
used to select the quadrant of a device to be placed on the PAEn bus. The most significant 3 bits, RDADD[7:5]
are again used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode.
Address bit RDADD[4] is don’t care during quadrant selection.
The REN input enables read operations from a selected Queue based on a rising edge of RCLK. A queue
to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless of the state
of REN. Data from a newly selected queue will be available on the Qout output bus on the second RCLK
cycle after queue selection regardless of REN. A read enable is not required to cycle the PAEn bus
(in polled mode) or to select the PAEn quadrant , (in direct mode).
If serial programming of the multi-queue device has been selected during master reset, the SCLK input
clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device
on the rising edge of SCLK provided that SENI is enabled, LOW. When expansion of devices is performed
the SCLK of all devices should be connected to the same source.
During serial programming of a multi-queue device, data loaded onto the SI input will be clocked into the
part (via a rising edge of SCLK), provided the SENI input of that device is LOW. If multiple devices are
cascaded, the SENI input should be connected to the SENO output of the previous device. So when serial
loading of a given device is complete, its SENO output goes LOW, allowing the next device in the chain
to be programmed (SENO will follow SENI of a given device once that device is programmed). The SENI
input of the master device (or single device), should be controlled by the user.
This output is used to indicate that serial programming or default programming of the multi-queue
device has been completed. SENO follows SENI once programming of a device is complete. Therefore,
SENO will go LOW after programming provided SENI is LOW, once SENI is taken HIGH again, SENO
will also go HIGH. When the SENO output goes LOW, the device is ready to begin normal read/write
operations. If multiple devices are cascaded and serial programming of the devices will be used, the SENO
output should be connected to the SENI input of the next device in the chain. When serial programming
of the first device is complete, SENO will go LOW, thereby taking the SENI input of the next device LOW
and so on throughout the chain. When a given device in the chain is fully programmed the SENO output
essentially follows the SENI input. The user should monitor the SENO output of the final device in the chain.
When this output goes LOW, serial loading of all devices has been completed.
During serial programming this pin is loaded with the serial data that will configure the multi-queue devices.
Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion
mode the serial data input is loaded into the first device in a chain. When that device is loaded and its SENO
has gone LOW, the data present on SI will be directly output to the SO output. The SO pin of the first device
connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers.
This output is used in expansion mode and allows serial data to be passed through devices in the chain
to complete programming of all devices. The SI of a device connects to SO of the previous device in the
chain. The SO of the final device in a chain should not be connected.
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge
of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs
to be tied to GND.
13
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009