IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet - Page 3

• Manufacturer Part Number: IDT72P51777L7-5BBI
• Description: IC FLOW CTRL 40BIT 376-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51777L7-5BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51777L7-5BBI

Figure 1. Multi-Queue Flow-Control Device Block Diagram ............................................................................................................................................. 6
Figure 2a. AC Test Load ................................................................................................................................................................................................ 18
Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 18
Figure 3. HSTL Termination for XGMII ........................................................................................................................................................................... 21
Figure 4. Reference Signals .......................................................................................................................................................................................... 22
Figure 5. Expansion for Unlimited Number of Multi-Queue Devices Example .................................................................................................................. 28
Figure 6. Device Programming Hierarchy ..................................................................................................................................................................... 29
Figure 7. DDR Read Operation with PLL ON ................................................................................................................................................................. 30
Figure 8. DDR Read Operation with PLL OFF ............................................................................................................................................................... 30
Figure 9. SDR Read Operation with PLL ON ................................................................................................................................................................. 31
Figure 10. SDR Read Operation with PLL OFF ............................................................................................................................................................. 31
Figure 11. Write Port Switching Queues Signal Sequence .............................................................................................................................................. 34
Figure 12. Switching Queues Bus Efficiency ................................................................................................................................................................... 34
Figure 13. Simultaneous Queue Switching ..................................................................................................................................................................... 35
Figure 14. Application: Reading words from the MQ using the EOP bit to end the read operation ..................................................................................... 36
Figure 15. Output Data during a Queue Switch (SDR w/o PLL) ...................................................................................................................................... 37
Figure 16. Output Data during a Queue Switch (SDR w/ PLL) ....................................................................................................................................... 38
Figure 17. Output Data during a Queue Switch (DDR w/ PLL) ....................................................................................................................................... 39
Figure 18. Output Data during a Queue Switch (DDR w/o PLL) ..................................................................................................................................... 40
Figure 19. Output Data during two Queue Switches (DDR w/ PLL) ................................................................................................................................ 41
Figure 20. Output Data during two Queue Switches (DDR w/o PLL) .............................................................................................................................. 42
Figure 21. Read Port Switching Queues Signal Sequence ............................................................................................................................................. 44
Figure 22. Switching Queues Bus Efficiency ................................................................................................................................................................... 44
Figure 23. Simultaneous Queue Switching ..................................................................................................................................................................... 45
Figure 24. MARK and Re-Write Sequence .................................................................................................................................................................... 46
Figure 25. MARK and Re-Read Sequence ................................................................................................................................................................... 46
Figure 26. MARKing a Queue - Write Queue MARK ...................................................................................................................................................... 47
Figure 27. MARKing a Queue - Read Queue MARK ..................................................................................................................................................... 47
Figure 28. UN-MARKing a Queue - Write Queue UN-MARK ......................................................................................................................................... 48
Figure 29. UN-MARKing a Queue - Read Queue UN-MARK ........................................................................................................................................ 48
Figure 30. Leaving a MARK active on the Write Port ...................................................................................................................................................... 49
Figure 31. Leaving a MARK active on the Read Port ..................................................................................................................................................... 49
Figure 32. Inactivating a MARK on the Write Port Active ................................................................................................................................................. 50
Figure 33. Inactivating a MARK on the Read Port Active ................................................................................................................................................ 50
Figure 34. DDR Source Synchronous Center Aligned Clocking .................................................................................................................................... 57
Figure 35. SDR Edge Aligned Clocking ........................................................................................................................................................................ 57
Figure 36. Bus-Matching Byte Arrangement .................................................................................................................................................................. 59
Figure 37. Master Reset ................................................................................................................................................................................................ 60
Figure 38. Default Programming .................................................................................................................................................................................... 61
Figure 39. Write Address/Read Address Programming ................................................................................................................................................... 62
Figure 40. Serial Port Connection for Serial Programming .............................................................................................................................................. 63
Figure 41. Serial Programming (2 Device Expansion) ................................................................................................................................................... 64
Figure 42. SDR Write Queue Select, Write Operation and Full Flag Operation ................................................................................................................ 65
Figure 43. DDR Write Operation, Write Queue Select, Full Flag Operation ...................................................................................................................... 66
Figure 44. Write Queue Select, Mark and Rewrite .......................................................................................................................................................... 67
Figure 45. Full Flag Timing in Expansion Configuration .................................................................................................................................................. 68
Figure 46. SDR Read Queue Select, Read Operation (IDT mode) ................................................................................................................................ 69
Figure 47. DDR Read Operation, Read Queue Select, EF & PAE Flag Operation ......................................................................................................... 70
Figure 48. Read Queue Select, Mark and Reread (IDT mode) ...................................................................................................................................... 71
Figure 49. Standard Mode Pointers on Queue Re-entry for DDR Read Operation ......................................................................................................... 72
Figure 50. BOI Mode Pointers on Queue Re-entry for DDR Read Operation ................................................................................................................. 72
Figure 51. Read Queue Selection with Read Operations (IDT mode) (SDR mode, PLL = OFF) ..................................................................................... 73
Figure 52. Read Queue Select, Read Operation and OE Timing .................................................................................................................................... 74
Figure 53. Almost Full Flag Timing and Queue Switch .................................................................................................................................................... 75
Figure 54. Almost Full Flag Timing ................................................................................................................................................................................. 75
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
List of Figures
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009