IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet - Page 21

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IDT72P51777L7-5BBI

Manufacturer Part Number
IDT72P51777L7-5BBI
Description
IC FLOW CTRL 40BIT 376-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT72P51777L7-5BBI

Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72P51777L7-5BBI

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Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72P51777L7-5BBI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
XGMII REFERENCE SPECIFICATION
can be applied within a variety of 10 Gb/s equipment types. The electrical
specifications are selected for an integrated circuit to integrated circuit application.
The electrical characteristics specified in this clause apply to all XGMII signals.
TABLE 2 — DC AND AC SPECIFICATIONS (INFORMATIVE)
TABLE 3 — IDT TO XGMII INTERFACE MAPPING SCHEMA
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
V
V
V
V
V
V
Input Port
- Input Port Data
- Input Port Enable
- Input Port Control
- Input Port Status
- Input Port Clock
Output Port
- Output Port Data
- Output Port Enable
- Output Port Control
- Output Port Status
- Output Port Clock
The XGMII uses 1.5V High Speed Transceiver Logic (HSTL) signal levels.
The electrical characteristics of the XGMII are specified such that the XGMII
Symbol
DDQ
REF
IH_DC
IL_DC
IH_AC
IL_AC
Signal Type
Output Voltage Supply
Input Reference Voltage
DC Input Logic High
DC Input Logic Low
AC Input Logic High
AC Input Logic Low
Parameter
Figure 3. HSTL Termination for XGMII
IDT Interface Signal
Nomenclature
V
V
Minimum
REF
REF
-0.30
D[32:39]
FF, PAF
Q[32:39]
EF, PAE
0.68
D[31:0]
Q[31:0]
1.4
WCLK
RCLK
WEN
REN
+0.10
+0.20
-
N/A
N/A
Nominal
0.75
1.5
VTT = Vddq/2
-
-
-
-
optional
21
r
When implemented as a chip-to-chip interface, the XGMII uses High Speed
Transceiver Logic (HSTL), specified for a 1.5 volt output buffer supply voltage.
XGMII chip-to-chip signals shall comply with EIA/JEDEC Standard EIA/JESD8-
6 using Class I, output buffers. Output impedance shall be greater than 38Ω to
assure acceptable overshoot and undershoot performance in an un-terminated
interconnection.
50 ohms
V
V
V
Maximum
REF
DDQ
Nomenclature
REF
XGMII Signal
User definable
User definable
0.90
1.6
RXD [31:0]
TXD [31:0]
RXC [3:0}
-
TXC[3:0]
RX_CLK
-0.20
TX_CLK
+0.3
-0.1
N/A
N/A
N/A
N/A
Units
V
V
V
V
V
V
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009

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