IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet - Page 5

• Manufacturer Part Number: IDT72P51777L7-5BBI
• Description: IC FLOW CTRL 40BIT 376-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51777L7-5BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51777L7-5BBI

DESCRIPTION
single chip solutions containing up to 128 configurable queues. All queues within
the device have a common data input bus, Din [39:0] (write port) and a common
data output bus Qout [39:0], (read port). Data written into the write port is directed
to a respective queue via an integrated de-multiplex function. Data read from
the read port is accessed from a given queue transparently via an internal
multiplex operation. Data writes and reads can be performed at high speeds
up to 166MHz DDR allowing data rates up to 10Gigabits/s (OC-192). By utilizing
high speed interfaces such as 1.5V HSTL, coupled with a x40 bit data bus and
10Mb of data storage, the 10G Multi-Queue can interface with the industry
standard 10 Gigabits/sec Media Independent Interface (XGMII) to allow high
speed data transmission over 10G Ethernet and SONET line cards. Data write
and read operations are totally independent of each other. The Write Clock and
Read Clock can operate at independent frequencies. A different queue may
be selected on the write port and read port or both ports may select the same
queue simultaneously. Multiple clocking schemes are offered for this device as
well. The user can utilize either single ended or differential clocking for DDR
read operations. DDR write operation utilize a single ended clock. SDR write
and read operations utilize a single ended clock.
for write and read operations respectively. Also a Programmable Almost Full
(PAF) and Programmable Almost Empty (PAE) flag for each queue is provided.
Two 8 bit programmable flag busses (PAFn, PAEn) are available, providing
status of queues that are not the present queue selected for write or read
operations. When 8 or fewer queues are configured in the device, these flag
busses provide an individual flag per queue, when more than 8 queues are
used; the queue status is multiplexed through the 8 stus lines. The multiplexing
can be configured either a Polled or Direct mode of bus.
bits wide. When Bus Matching is used the device ensures the logical transfer
of data throughput. . With a 40 data bits configuration parity checking and packet
tagging is achievable if desired. Parity checking is available through the use of
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
The IDT72P51767/ IDT72P51777 multi-queue flow-control devices are
The devices provide Full flag and Empty flag status for the queue selected
Bus Matching is available on this device; either port can be x20 bits or x40
5
4 user selectable bits as part of the 40 bit word. The user will be able to pass
along parity bits through the Multi-Queue to use for error detection in a up/down
stream device. The Multi-Queue device does not provide parity checking
circuits.
last pipelined data word that is stored in the output register which in IDT standard
mode is required to be read out during a queue switch . The last pipelined data
word in BOI mode is retained in the output data register until it is actively read.
write and read ports respectively. These functions allows for a mark location to
be independently issued on the read and/or write ports, in their respective
queues. The option to reset a given queue to the mark location effectively
dropping data written into the queue or allow data to be read again from the
device.
queues configured at start-up, which means the user can program the number
of queues to divide the 10Mb/5Mb of memory depending on the device. The
Multi-Queues can even be programmed to support one single queue to be used
as a FIFO for high performance applications of sequential queuing. The
programmable flag positions are also user programmable. If the user does not
wish to program the multi-queue device, a default option is available that
configures the device in a predetermined manner. A Master Reset latches in
all configuration setup pins and must be performed before programming of the
device can take place.
in either 1.5V HSTL , or 1.8V eHSTL mode. The type of I/O is selected via the
IOSEL input. The core supply voltage (VCC) to the multi-queue is always 1.8V,
however the output levels can be set independently via a separate supply,
VDDQ. The package used will be a 23mm x 23mm, BB-376 BGA package for
better noise immunity and ground bounce prevention.
a fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture.
In Back off One mode, the user can switch queues without having to read the
A Mark and Re-write and a Mark and Re-read function are available on the
The devices offer a default configuration upon reset, offering 128 symmetrical
The multi-queue flow-control devices have the capability of operating its I/O
A JTAG test port is provided, here the multi-queue flow-control device has
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009