IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet - Page 53

• Manufacturer Part Number: IDT72P51777L7-5BBI
• Description: IC FLOW CTRL 40BIT 376-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51777L7-5BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51777L7-5BBI

ALMOST FULL FLAG
single Programmable Almost Full flag output, PAF. The PAF flag output provides
a status of the almost full condition for the active queue currently selected on the
write port for write operations. Internally the multi-queue flow-control device
monitors and maintains a status of the almost full condition of all queues within
it, however only the queue that is selected for write operations has its full status
output to the PAF flag. This dedicated flag is often referred to as the “active queue
almost full flag”. The position of the PAF flag boundary within a queue can be
at any point within that queues depth. This location can be user programmed
via the serial port or one of the default values (8 or 128) can be selected if the
user has performed default programming.
full status, when a queue is selected on the write port, this status is output via the
PAF flag. The PAF flag value for each queue is programmed during multi-queue
device programming (along with the number of queues, queue depths and
almost empty values). The PAF offset value, m, for a respective queue can be
programmed to be anywhere between ‘0’ and ‘D’, where ‘D’ is the total memory
depth for that queue. The PAF value of different queues within the same device
can be different values.
will switch to the new queue and provide the user with the new queue status,
on the third cycle after a new queue selection is made, on the same WCLK cycle
that data can actually be written to the new queue. That is, a new queue can
be selected on the write port via the WRADD bus, WADEN enable and a rising
edge of WCLK. On the third rising edge of WCLK following a queue selection,
the PAF flag output will show the full status of the newly selected queue. The PAF
is flag output is double register buffered, so when a write operation occurs at
the almost full boundary causing the selected queue status to go almost full the
PAF will go LOW 3 WCLK cycles after the write. The same is true when a read
occurs, there will be a 3 WCLK cycle delay after the read operation.
t
t
occur based on a rising edge of WCLK. Internally the multi-queue device
monitors and keeps a record of the almost full status for all queues. It is possible
that the status of a PAF flag maybe changing internally even though that flag is
not the active queue flag (selected on the write port). A queue selected on the
read port may experience a change of its internal almost full flag status based
on read operations. The multi-queue flow-control device also provides a
duplicate of the PAF flag on the PAF[7:0] flag bus, this will be discussed in detail
in a later section of the data sheet.
ALMOST EMPTY FLAG
single Programmable Almost Empty flag output, PAE. The PAE flag output
provides a status of the almost empty condition for the active queue currently
selected on the read port for read operations. Internally the multi-queue flow-
control device monitors and maintains a status of the almost empty condition of
all queues within it, however only the queue that is selected for read operations
has its empty status output to the PAE flag. This dedicated flag is often referred
to as the “active queue almost empty flag”. The position of the PAE flag boundary
within a queue can be at any point within that queues depth. This location can
be user programmed via the serial port or one of the default values (8 or 128)
can be selected if the user has performed default programming.
WAF.
WAF.
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
As previously mentioned the multi-queue flow-control device provides a
As mentioned, every queue within a multi-queue device has its own almost
When queue switches are being made on the write port, the PAF flag output
So the PAF flag delay from a write operation to PAF flag LOW is 3 WCLK +
Note, if t
The PAF flag is synchronous to the WCLK and all transitions of the PAF flag
See Figures 23 and 24 for Almost Full flag timing and queue switching.
As previously mentioned the multi-queue flow-control device provides a
The delay from a read operation to PAF flag HIGH is t
SKEW
is violated there will be one added WCLK cycle delay.
SKEW2
+ WCLK +
53
empty status, when a queue is selected on the read port, this status is output via
the PAE flag. The PAE flag value for each queue is programmed during multi-
queue device programming (along with the number of queues, queue depths
and almost full values). The PAE offset value, n, for a respective queue can be
programmed to be anywhere between ‘0’ and ‘D’, where ‘D’ is the total memory
depth for that queue. The PAE value of different queues within the same device
can be different values.
will switch to the new queue and provide the user with the new queue status,
on the third cycle after a new queue selection is made, on the same RCLK cycle
that data actually falls through to the output register from the new queue. That
is, a new queue can be selected on the read port via the RDADD bus, RADEN
enable and a rising edge of RCLK. On the third rising edge of RCLK following
a queue selection, the data word from the new queue will be available at the
output register and the PAE flag output will show the empty status of the newly
selected queue. The PAE is flag output is double register buffered, so when a
read operation occurs at the almost empty boundary causing the selected queue
status to go almost empty the PAE will go LOW 3 RCLK cycles after the read.
The same is true when a write occurs, there will be a 3 RCLK cycle delay after
the write operation.
t
t
occur based on a rising edge of RCLK. Internally the multi-queue device
monitors and keeps a record of the almost empty status for all queues. It is possible
that the status of a PAE flag maybe changing internally even though that flag is
not the active queue flag (selected on the read port). A queue selected on the
write port may experience a change of its internal almost empty flag status based
on write operations. The multi-queue flow-control device also provides a
duplicate of the PAE flag on the PAE[7:0] flag bus, this will be discussed in detail
in a later section of the data sheet.
PAFn - DIRECT BUS
mode. In direct mode the user can address the status word of queues they
require and it will be placed on to the PAFn bus. For example, consider the
operation of the PAFn bus when 26 queues have been setup. To output status
of the first status word, Queue[0:7] the WRADD bus is used in conjunction with
the FSTR (PAF flag strobe) input and WCLK. The address present on the 4
least significant bits of the WRADD bus with FSTR HIGH will be selected as the
status word address on a rising edge of WCLK. To address status word 0,
Queue[0:7] the WRADD bus should be loaded with “0010000”, the PAFn bus
will change status to show the new status word selected 1 WCLK cycle after status
word selection. PAFn[0:7] gets status of queues, Queue[0:7] respectively.
PAFn[0:7] gets status of queues, Queue[8:15] respectively. To address the 2nd
status word, Queue[16:23], the WRADD address is “00100010”. PAF[0:7] gets
status of queues, Queue[16:23] respectively. To address the 3rd status word,
Queue[24:31], the WRADD address is “00100011”. PAF[0:1] gets status of
queues, Queue[24:25] respectively. Remember, only 26 queues were setup,
so when status word 4 is selected the unused outputs PAF[2:7] will be don't care
states.
queue ‘x’ on the same cycle as a status word switch which will include the queue
RAE
RAE.
As mentioned, every queue within a multi-queue device has its own almost
When queue switches are being made on the read port, the PAE flag output
So the PAE flag delay from a read operation to PAE flag LOW is 3 RCLK +
Note, if t
The PAE flag is synchronous to the RCLK and all transitions of the PAE flag
See Figures 25 and 26 for Almost Empty flag timing and queue switching.
If FM is LOW at master reset then the PAFn bus operates in Direct (addressed)
To address status word 1, Queue[8:15], the WRADD address is “00100001”.
Note, that if a read or write operation is occurring to a specific queue, say
. The delay from a write operation to PAE flag HIGH is t
SKEW
is violated there will be one added RCLK cycle delay.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009
SKEW2
+ RCLK +