IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet - Page 14

• Manufacturer Part Number: IDT72P51777L7-5BBI
• Description: IC FLOW CTRL 40BIT 376-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51777L7-5BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51777L7-5BBI

PIN DESCRIPTIONS (CONTINUED)
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
TDI
(A11)
TDO
(B11)
TP
(U3)
TMS
(A10)
TRST
(A9)
WADEN
(M3)
WCLK
(M2)
WCS
(L1)
WEN
(M1)
WRADD[7:0]
(WRADD7-R2 Bus
WRADD6-R1
WRADD5-P3
WRADD4-P2
WRADD3-P1
WRADD2-N3
WRADD1-N2
WRADD0-N1)
ZQ
(N22)
Symbol &
(Pin No.)
JTAG Test Data
JTAG Test Data
Output
IDT Internal
Test Pin
JTAG Mode
Select
JTAG Reset
Write Address
Enable
Write Clock
Write Chip
Select
Write Enable
Write Address
ZQ
Name
I/O TYPE
INPUT
LVTTL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
operation, Input test data serially loaded via the TDI on the rising edge of TCK to either the Instruction
Register, ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected
operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction
Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in
SHIFT-DR and SHIFT-IR controller states.
For IDT internal test purpose only, must be tied to GND for normal/correct operation.
TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not
automatically reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for
five TCK cycles. If the TAP controller is not properly reset then the outputs will always be in high-impedance.
If the JTAG function is used but the user does not want to use TRST, then TRST can be tied with MRS
to ensure proper queue operation. If the JTAG function is not used then this signal needs to be tied to GND.
An internal pull-up resistor forces TRST HIGH if left unconnected.
The WADEN input is used in conjunction with WCLK and the WRADD address bus to select a queue to
be written in to. A queue addressed via the WRADD bus is selected on the rising edge of WCLK provided
that WADEN is HIGH. WADEN should be asserted (HIGH) only during a queue change cycle(s). WADEN
should not be permanently tied HIGH. WADEN cannot be HIGH for the same WCLK cycle as FSTR. Note,
that a write queue selection cannot be made, (WADEN must NOT go active) until programming of the part
has been completed and SENO has gone LOW.
When enabled by WEN, the rising edge of WCLK writes data into the selected Queue via the input bus,
Din. The Queue to be written to is selected via the WRADD address bus and a rising edge of WCLK while
WADEN is HIGH. A rising edge of WCLK in conjunction with FSTR and WRADD will also select the flag
quadrant to be placed on the PAFn bus during direct flag operation. During polled flag operation the PAFn
bus is cycled with respect to WCLK and the FSYNC signal is synchronized to WCLK. The PAFn, PAF and
FF outputs are all synchronized to WCLK. During device expansion the FXO and FXI signals are based
on WCLK. The WCLK must be continuous and free-running
The WCS signal in concert with WEN signal provides control to enable data from the input write data bus
to be written into the device. During a Master Reset cycle the WCS it is don’t care signal.
The WEN input enables write operations to a selected Queue based on a rising edge of WCLK. A queue
to be written to can be selected via WCLK, WADEN and the WRADD address bus regardless of the state
of WEN. Data present on Din can be written to a newly selected queue on the second WCLK cycle after
queue selection provided that WEN is LOW. A write enable is not required to cycle the PAFn bus (in polled
mode) or to select the PAFn quadrant , (in direct mode).
The WRADD bus is 8 bits. The WRADD bus is a dual purpose address bus. The first function of WRADD
is to select a Queue to be written to. The least significant 5 bits of the bus, WRADD[4:0] are used to address
to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. These 3 MSB’s
will address a device with the matching ID code. (See ID[2:0] description for more detail on matching ID
code. The second function of the WRADD bus is to select the quadrant of queues to be loaded on to the
PAFn bus during strobed flag mode. The least significant 4 bits, WRADD[3:0] are used to select the quadrant
of a device to be placed on the PAFn bus. The most significant 3 bits, WRADD[7:5] are again used to select
is don’t care during quadrant selection.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. Q[39:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ
and ground. This pin cannot be connected directly to GND or left unconnected.
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
1 of 128 possible queues within a multi-queue device. The most significant 3 bits, WRADD[7:5] are used
1 of 8 possible multi-queue devices that may be connected in expansion mode. Address bit WRADD[4]
14
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009