MAX17080GTL+ Maxim Integrated Products, MAX17080GTL+ Datasheet - Page 44

• Manufacturer Part Number: MAX17080GTL+
• Description: IC CONTROLLER AMD SVI 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17080GTL+

• Applications: Controller, AMD SVI
• Voltage - Input: 2.7 ~ 5.5 V
• Number Of Outputs: 3
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

AMD 2-/3-Output Mobile Serial
VID Controller
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit. The
device that acknowledges has to pull down the SVD
line during the acknowledge clock pulse so that the
SVD line is stable low during the high period of the
acknowledge-related clock pulse. Of course, setup and
hold times must be taken into account. See Figure 12.
A complete command consists of a START condition
(S) followed by the MAX17080’s slave address and a
data phase, followed by a STOP condition (P). For the
slave address, bits 6:4 are always 110 and bit 3 is X
(don’t care). The WR bit should always be 1 since read
functions are not supported. Figure 13 is the SVI bus
data-transfer summary. Table 8 is a description of the
SVI send byte address and Table 9 describes serial
VID 8-bit field encoding.
The minimum input operating voltage (drop-out voltage)
is restricted by stability requirements, not the minimum
off-time (t
slope compensation, so the controller becomes unsta-
ble with duty cycles greater than 50% per phase:
However, the controller can briefly operate with duty
cycles over 50% during heavy load transients.
Table 8. SVI Send Byte Address Description
44
BIT
6:4
3
2
1
0
______________________________________________________________________________________
SMPS Applications Information
OFF(MIN)
Always 110b.
X—don’t care.
VDD1, if set then the following data byte contains
the VID for VDD1. Bit 2 is ignored in combined
mode (GNDS1 or GNDS2 = V
to CORE1 of the AMD CPU.
VDD0, if set then the following data byte contains
the VID for VDD0 in separate mode, and the
unified VDD in combined mode. VDD0 refers to
CORE0 of the AMD CPU.
VDDNB, if set then the following data byte
contains the VID for VDDNB.
V
IN(MIN)
). The MAX17080 does not include
≥ 2V
DESCRIPTION
OUT(MAX)
Minimum Input Voltage
Duty-Cycle Limits
DDIO
Command Byte
). VDD1 refers
Acknowledge
The MAX17080 controller has a minimum on-time,
which determines the maximum input operating voltage
that maintains the selected switching frequency. With
higher input voltages, each pulse delivers more energy
than the output is sourcing to the load. At the beginning
of each cycle, if the output voltage is still above
the feedback threshold voltage, the controller does not
trigger an on-time pulse, resulting in pulse-skipping
operation regardless of the operating mode selected by
PSI_L. This allows the controller to maintain regulation
above the maximum input voltage, but forces the con-
troller to effectively operate with a lower switching fre-
quency. This results in an input threshold voltage at
which the controller begins to skip pulses (V
:
where f
the OSC resistor, and t
driver’s turn-on delay (DL low to DH high). For the best
high-voltage performance, use the slowest switching
frequency setting (100kHz per phase, R
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention (Figure 14). If
possible, mount all the power components on the top
side of the board with their ground terminals flush
against one another, and mount the controller and ana-
log components on the bottom layer so the internal
ground layers shield the analog components from any
Table 9. Serial VID 8-Bit Field Encoding
BIT
6:0
7
SW
PSI_L: Power-Save Indicator
0 means the processor is at an optimal load and
the SMPS(s) can enter power-saving mode. The
SMPS operates in pulse-skipping mode after
exiting the boot mode. Offset is disabled if
previously enabled by the OPTION pin. The
MAX17080 enters 1-phase operation if in
combined mode (GNDS1 or GNDS2 = H).
1 means the processor is in a high current-
consumption state. The SMPS operates in forced-
PWM mode after exiting the boot mode. Offset is
enabled if previously enabled by the OPTION
pin. The MAX17080 returns to 2-phase operation
if in combined mode (GNDS1 or GNDS2 = H).
SVID[6:0] as defined in Table 7.
is the per-phase switching frequency set by
V
IN SKIP
(
)
=
ON(MIN)
V
OUT
DESCRIPTION
PCB Layout Guidelines
⎛
⎜
⎜
⎝
f
SW ON MIN
Maximum Input Voltage
is 150ns (max) minus the
t
1
(
OSC
)
⎞
⎟
⎟
⎠
IN(SKIP)
= 432kΩ).
):