MAX17080GTL+ Maxim Integrated Products, MAX17080GTL+ Datasheet - Page 39

• Manufacturer Part Number: MAX17080GTL+
• Description: IC CONTROLLER AMD SVI 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17080GTL+

• Applications: Controller, AMD SVI
• Voltage - Input: 2.7 ~ 5.5 V
• Number Of Outputs: 3
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

The input capacitor must meet the ripple-current
requirement (I
For a dual 180° interleaved controller, the out-of-phase
operation reduces the RMS input ripple current, effec-
tively lowering the input capacitance requirements.
When both outputs operate with a duty cycle less than
50% (V
defined by the following equation:
where I
In combined mode (GNDS1 = V
V
simplifies to:
For most applications, nontantalum chemistries (ceram-
ic, aluminum, or OS-CON) are preferred due
to their resistance to inrush surge currents typical of
systems with a mechanical switch or connector in
series with the input. If the MAX17080 is operated as
the second stage of a two-stage power-conversion sys-
tem, tantalum input capacitors are acceptable. In either
configuration, choose an input capacitor that exhibits
less than +10°C temperature rise at the RMS input cur-
rent for optimal circuit longevity.
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the output
capacitance and processor’s power-dissipation require-
ments. The controller uses a transconductance amplifier
to set the transient AC and DC output-voltage droop
(Figure 4). The FBAC and FBDC configuration adjusts
the steady-state regulation voltage as a function of the
load. This adjustability allows flexibility in the selected
current-sense resistor value or inductor DCR, and allows
smaller current-sense resistance to be used, reducing
the overall power dissipated.
The inductor current ripple sensed across the current-
sense inputs (CSP_ - CSN_) generates a proportionate
current out of the FBAC pin. This AC current flowing
across the effective impedance at FBAC generates an
AC ripple voltage. Actual stability, however, depends
on the AC voltage at the FBDC pin, and not on the
I
RMS
DDIO
Core Voltage Positioning and Loop Compensation
=
) with both phases active, the input RMS current
IN
IN
⎛
⎝ ⎜
V
is the average input current:
OUT
V
I
> 2V
IN
IN
I
RMS
1
=
RMS
⎞
⎠ ⎟
⎛
⎝ ⎜
I
OUT
OUT
V
=
______________________________________________________________________________________
) imposed by the switching currents.
OUT
V
Core Transient Droop and Stability
I
OUT
1
IN
), the RMS input ripple current is
(
I
OUT
1
Core Input Capacitor Selection
⎞
⎠ ⎟
1
⎛
⎜
⎝
I
OUT
−
V
OUT
V
I
IN
IN
)
1
+
+
⎞
⎟
⎠
⎛
⎝ ⎜
⎛
⎜
⎝
⎛
⎝ ⎜
V
2
1
V
OUT
V
−
I
OUT
V
N N
DDIO
IN
V
2
OUT
V
⎞
⎠ ⎟
IN
2
I
OUT
⎞
⎠ ⎟
or GNDS2 =
I
⎞
⎟
⎠
OUT
AMD 2-/3-Output Mobile Serial
2
(
I
OUT
2
2
−
I
IN
)
FBAC pin. Based on the configuration shown in Figure
4, the ripple voltage at the FBDC pin can only be less
than, or equal to, the ripple at the FBAC pin.
With the requirement that R
(Z
where Gm
Electrical Characteristics table, R
value of the current-sense element that is used to pro-
vide the (CSP_, CSN_) current-sense voltage, and f
is the selected switching frequency.
Based on the above requirement for R
and with the other requirement for R
Core Steady-State Voltage Positioning (DC Droop) sec-
tion, R
AC droop is:
Capacitor C
than R
equation:
With R
positioning slope, R
or at most equal to, R
Choose the R
sen, then select R
DC droop is typically used together with the +12.5mV
offset feature to keep within the DC tolerance window of
the application. See the Offset and Address Change for
Core SMPSs (OPTION) section.
Most of the following MOSFET guidelines focus on the
challenge of obtaining high-load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention.
The high-side MOSFET (N
the resistive losses plus the switching losses at both
V
IN(MIN)
CFB
R
R
R
//R
DROOP DC
DROOP_AC
DROOP AC
FBAC
FBAC
DROOP_AC
C
FB
and V
FB
) < 10% of R
(FBAC_)
FB
×
and R
=
_
_
FBDC
⎡ ⎣
R
Core Steady-State Voltage Positioning
is required when the R
R
IN(MAX)
FBDC
. Choose C
FB
=
FB
≈
FBDC
defined, the steady-state voltage-
/ /(
is typically 2mS as defined in the
R
and R
R
DROOP_DC
R
to give the desired droop.
FBAC
VID Controller
DROOP_AC
FBDC FBAC SENSE
FBDC FBAC SENSE
≥
R
R
Core Power-MOSFET Selection
. Calculate both of these sums.
FBAC
FBAC
C
FBAC
can be chosen. The resultant
OUT SW SENSE
FBAC
R
H
R
+
FB
) must be able to dissipate
R
, then:
+
f
+
FBDC
R
according to the following
R
, can only be less than,
FBDC
:
already previously cho-
FBDC
R
FBDC
R
R
SENSE_
+
1
FBDC
)
R
DROOP_DC
⎤ ⎦ = ×
FBAC
FB
= R
Gm
Gm
is the effective
3
Gm
defined in the
(
FBAC
FBAC
and R
(
FBA
t
( (
SW
FBAC
C C )
)
is less
, and
FBDC
)
SW
39
,