MAX17080GTL+ Maxim Integrated Products, MAX17080GTL+ Datasheet - Page 28

• Manufacturer Part Number: MAX17080GTL+
• Description: IC CONTROLLER AMD SVI 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17080GTL+

• Applications: Controller, AMD SVI
• Voltage - Input: 2.7 ~ 5.5 V
• Number Of Outputs: 3
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

AMD 2-/3-Output Mobile Serial
VID Controller
controller reaches the target output voltage. At the end
of a downward VID transition, the upper PWRGD thresh-
old is enabled only after the output reaches the lower
VID code setting. Figure 5 shows VID transition timing.
The MAX17080 automatically controls the current to the
minimum level required to complete the transition in the
calculated time. The slew-rate controller uses an inter-
nal capacitor and current source programmed by
R
tion time depends on R
the accuracy of the slew-rate controller (C
accuracy). The slew rate is not dependent on the total
output capacitance, as long as the surge current is less
than the current limit set by ILIM12 for the core SMPSs
and ILIM3 for the NB SMPS. For all dynamic positive
VID transitions or negative VID transitions in forced-
PWM mode (PSI_L set to 1), the transition time (t
is given by:
where dV
slew rate, V
is the new target voltage. See the Slew-Rate Accuracy
in the Electrical Characteristics table for slew-rate limits.
The output voltage tracks the slewed target voltage,
making the transitions relatively smooth. The average
inductor current per phase required to make an output
voltage transition is:
where dV
is the total output capacitance of each phase.
If the SMPS is in a pulse-skipping mode (PSI_L set to
0), the discharge rate of the output voltage during
downward transitions is then dependent on the load
current and total output capacitance for loads less than
a minimum current, and dependent on the R
grammed slew rate for heavier loads. The critical load
current (I
dent on the load is:
For load currents less than I
time is:
For soft-start, the controller uses a fixed slew rate of
1mV/µs. In shutdown, the outputs are discharged using
28
TIME
______________________________________________________________________________________
to transition the output voltage. The total transi-
I
LOAD(CRIT)
TARGET
LOAD CRIT
TARGET
OLD
t
I
L
TRAN
(
is the original output voltage, and V
t
≅
TRAN
/dt = 6.25mV/µs × 143kΩ/R
/dt is the required slew rate and C
C
)
OUT
) where the transition time is depen-
≅
≅
C
=
C
TIME
OUT
×
OUT
(
⎡ ⎣
V
dV
(
NEW
dV
, the voltage difference, and
I
×
TARGET
LOAD
×
TARGET
dV
LOAD(CRIT)
(
dV
−
TARGET
V
TARGET
OLD
/
dt
/
dt
⎤ ⎦
)
)
, the transition
/
dt
)
TIME
TIME
TRAN
SLEW
is the
NEW
OUT
pro-
)
a 20Ω switch through the CSN_ pins for the core
SMPSs and through the OUT3 pin for the NB SMPS.
After exiting the boot mode and if the PSI_L bit is set to
1, the MAX17080 operates with the low-noise, forced-
PWM control scheme. Forced-PWM operation disables
the zero-crossing comparator, forcing the low-side
gate-drive waveforms to constantly be the complement
of the high-side gate-drive waveforms. This keeps the
switching frequency constant and allows the inductor
current to reverse under light loads, providing fast,
accurate negative output-voltage transitions by quickly
discharging the output capacitors.
Forced-PWM operation comes at a cost: the no-load +5V
bias supply current remains between 50mA to 70mA,
depending on the external MOSFETs and switching fre-
quency. To maintain high efficiency under light load
conditions, the processor could switch the controller to a
low-power pulse-skipping control scheme.
During soft-start and in power-saving mode—when the
PSI_L bit is set to 0—the MAX17080 operates in pulse-
skipping mode. Pulse-skipping mode enables the driver’s
zero-crossing comparator, so the driver pulls its DL low
when “zero” inductor current is detected (V
0). This keeps the inductor from discharging the output
capacitors and forces the controller to skip pulses under
light load conditions to avoid overcharging the output.
In pulse-skipping operation, the controller terminates
the on-time when the output voltage exceeds the feed-
back threshold and when the current-sense voltage
exceeds the idle-mode current-sense threshold (V
= 0.15 x V
I
conditions, the continuous inductor current remains
above the idle-mode current-sense threshold, so the
on-time depends only on the feedback voltage thresh-
old. Under light load conditions, the controller remains
above the feedback voltage threshold, so the on-time
duration depends solely on the idle-mode current-
sense threshold, which is approximately 15% of the full-
load peak current-limit threshold set by ILIM12 for the
core SMPSs and 25% of the full-load peak current-limit
threshold set by ILIM3 for the NB SMPS.
During downward VID transitions, the controller tem-
porarily sets the OVP threshold of the SMPSs to 1.85V
(typ), preventing false OVP faults. Once the error ampli-
fier detects that the output voltage is in regulation, the
OVP threshold tracks the selected VID DAC code.
LX3PK
setting for the NB SMPS). Under heavy load
LIMIT
for the core SMPS and I
Pulse-Skipping Operation
Forced-PWM Operation
LX3MIN
GND
= 0.25 x
- V
LX
IDLE
=