MAX17080GTL+ Maxim Integrated Products, MAX17080GTL+ Datasheet - Page 32

• Manufacturer Part Number: MAX17080GTL+
• Description: IC CONTROLLER AMD SVI 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17080GTL+

• Applications: Controller, AMD SVI
• Voltage - Input: 2.7 ~ 5.5 V
• Number Of Outputs: 3
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

AMD 2-/3-Output Mobile Serial
VID Controller
Figure 7. Startup Sequence
The NB current sense is achieved by sensing the volt-
age across the high-side internal MOSFET during the
on-time. The current information is computed by dividing
the sensed voltage by the MOSFET’s on-resistance,
R
When the core SMPSs are configured in combined
mode (GNDS1 or GNDS2 pulled to V
MAX17080 current-mode architecture automatically
forces the individual phases to remain current bal-
anced. SMPS1 is the main voltage-control loop, and
SMPS2 maintains the current balance between the
phases. This control scheme regulates the peak induc-
tor current of each phase, forcing them to remain prop-
erly balanced. Therefore, the average inductor current
variation depends mainly on the variation in the current-
sense element and inductance value.
The MAX17080 current-limit circuit employs a fast peak
inductor current-sensing algorithm. Once the current-
sense signal of the SMPS exceeds the peak current-limit
threshold, the PWM controller terminates the on-time.
32
ON(NH3)
______________________________________________________________________________________
.
(VDD_PLANE_STRAP)
GNDS1 OR GNDS2
SMPS V
SVC/SVD
RESET_L
PWRGD
PGD_IN
DC_IN
SHDN
V
Combined-Mode Current Balance
DDIO
OUT
NB SMPS Current Sense
Peak Current Limit
1
2
DDIO
2-BIT BOOT VID
20µs
), the
3
4
SERIAL MODE
See the Core Peak Inductor Current Limit (ILIM12) sec-
tion in the Core SMPS Design Procedure section.
Power-on reset (POR) occurs when V
approximately 3V, resetting the fault latch and prepar-
ing the controller for operation. The V
lockout (UVLO) circuitry inhibits switching until V
rises above 4.25V (typ). The controller powers up the
reference once the system enables the controller V
above 4.25V and SHDN is driven high. With the refer-
ence in regulation, the controller ramps the SMPS and
NB voltages to the boot voltage set by the SVC and
SVD inputs:
The soft-start circuitry does not use a variable current
limit, so full output current is available immediately.
PWRGD becomes high impedance approximately 20µs
after the SMPS outputs reach regulation. The boot VID
is stored the first time PWRGD goes high. The
MAX17080 is in pulse-skipping mode during soft-start.
Figure 7 shows the MAX17080 startup sequence.
10µs
5
Power-Up Sequence (POR, UVLO, PGD_IN)
6
HIGH-Z
BLANK
7
20µs
8
t
START
BUS IDLE
=
(
1
V
mV s
BOOT
/µ
)
CC
CC
undervoltage-
rises above
CC
CC