MAX17080GTL+ Maxim Integrated Products, MAX17080GTL+ Datasheet - Page 25

• Manufacturer Part Number: MAX17080GTL+
• Description: IC CONTROLLER AMD SVI 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17080GTL+

• Applications: Controller, AMD SVI
• Voltage - Input: 2.7 ~ 5.5 V
• Number Of Outputs: 3
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

When a transient occurs, the output voltage deviation
depends on the controller’s ability to quickly detect the
transient and slew the inductor current. A fixed-frequency
controller typically responds only when a clock edge
occurs, resulting in a delayed transient response. To
minimize this delay time, the MAX17080 includes
enhanced transient detection and transient phase
repeat capabilities. If the controller detects that the out-
put voltage has dropped by 38mV, the transient detec-
tion comparator immediately retriggers the phase that
completed its on-time last. The controller triggers the
subsequent phases as normal, on the appropriate
oscillator edges. This effectively triggers a phase a full
cycle early, increasing the total inductor-current slew
rate and providing an immediate transient response.
The MAX17080 provides an FBAC and FBDC pin for
each SMPS to allow for flexible AC and DC droop set-
tings. FBAC is the output of an internal transconduc-
tance amplifier that outputs a current proportional to the
current-sense signal. FBDC is the feedback input that is
compared against the internal target. Place resistors
and capacitors at the FBAC and FBDC pins as shown
in Figure 4. With this configuration, the DC droop is
always less than or equal to the AC droop.
Figure 4. MAX17080 Core SMPS Feedback Connection
FBDC is the feedback input to the error amplifier.
Based on the configuration in Figure 4, the core SMPS
output voltage is given by:
where the target voltage (V
Nominal Output-Voltage Selection section, and the
FBAC amplifier’s output current (I
by each phase’s current-sense voltage:
Core Steady-State Voltage Positioning (DC Droop)
TARGET
CSN
CSP
V
OUT
MAX17080
ERROR
AMP
=
Gm
V
(FBAC)
TARGET
______________________________________________________________________________________
FBAC
FBDC
−
R
FBAC
C
FB
R
Adjustment Amplifiers
FBDC
Core SMPS Feedback
R
TARGET
FB
+
Transient Phase Repeat
R
R
R
×
FBDC
FBAC
FBDC
R
FBAC
FBAC
) is defined in the
AGND
+
R
) is determined
4700pF
100Ω
FB
AMD 2-/3-Output Mobile Serial
×
I
FB
CORE SENSE_H
A A C
where V
voltage, and Gm
Electrical Characteristics table. DC droop is typically used
together with the +12.5mV offset feature to keep within the
DC tolerance window of the application. See the Offset
and Address Change for Core SMPSs (OPTION) section.
The ripple voltage on FBDC must be less than the -28mV
(max) transient phase repeat threshold:
where ∆I
effective output ESR at the remote sense point, R
is the current-sense element, and Gm
(max) as defined in the Electrical Characteristics table.
The worst-case inductor ripple occurs at the maximum
input-voltage and maximum output-voltage conditions:
To make the DC and AC load-lines the same, directly
short FBAC to FBDC.
To disable DC voltage positioning, remove R
connects FBAC to FBDC.
Each of the MAX17080 core supply SMPSs includes one
transconductance amplifier for voltage positioning. The
amplifiers’ inputs are generated by summing their respec-
tive current-sense inputs, which differentially sense the
voltage across either current-sense resistor or the induc-
tor’s DCR.
The voltage-positioning amplifier’s output (FBAC) con-
nects to the remote-sense point of the output through
an R and C network that sets each phase’s AC voltage-
positioning gain:
where the target voltage (V
Nominal Output-Voltage Selection section, Z
effective impedance of C
output current (I
current-sense voltage:
V
R
OUT
FBAC
∆I
+
=
R
L MAX
CS
Core Transient Voltage-Positioning Amplifier
FBAC
R
(
V
FBDC
L
TARGET
R
= V
is the inductor ripple current, R
FBDC
)
+
CSP
=
R
(FBAC)
FB
≤
V
FBAC
I
I
OUT MAX
FBAC
R
FBAC
-
- V
∆
(
FBAC
R
56
I R
L SENSE
FBAC
VID Controller
CSN
mV
(
) is determined by each phase’s
is typically 2mS as defined in the
∆
=
=
2
I R
-
L SENSE
Gm
Gm
∆
FB
is the differential current-sense
R
)
+
I R
V
Gm
L ESR
(
FBDC
IN M
V
R
, and the FBAC amplifier’s
(
TARGET
FBAC CS
IN MAX
(
FBDC
(
FBAC CS
(
FBAC FBDC
(
Gm
A A X SW
)
(
×
R
)
)
)
(
FBAC
V
FBAC
R
)
R
f
+
V
)
FBAC
) is defined in the
−
R
FB
L
(FBAC)
V
)
+
OUT MAX
- 56
R
+
F
∆ ∆ I R
B B
mV
Z
L ESR
)
(
(AC Droop)
CF
ESR
CFB
is 2.06mS
FB
B B
)
, which
I
≤
)
FBAC
SENSE
is the
is the
28
mV
25