MAX17080GTL+ Maxim Integrated Products, MAX17080GTL+ Datasheet - Page 24

• Manufacturer Part Number: MAX17080GTL+
• Description: IC CONTROLLER AMD SVI 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17080GTL+

• Applications: Controller, AMD SVI
• Voltage - Input: 2.7 ~ 5.5 V
• Number Of Outputs: 3
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

AMD 2-/3-Output Mobile Serial
VID Controller
The MAX17080 consists of a dual fixed-frequency PWM
controller with external switches that generate the sup-
ply voltage for two independent CPU cores, and one
low-input-voltage internal switch SMPS for the separate
NB SMPS. The CPU core SMPSs can be configured as
independent outputs, or as a combined output by con-
necting the GNDS1 or GNDS2 pin-strap high (GNDS1
or GNDS2 pulled to 1.5V to 1.8V, which are the respec-
tive voltages for DDR3 and DDR2).
All three SMPSs can be programmed independently to
any voltage in the VID table (see Table 4) using the serial
VID interface (SVI). The CPU is the SVI bus master, while
the MAX17080 is the SVI slave. Voltage transitions are
commanded by the CPU as a single step command from
one VID code to another. The MAX17080 slews the
SMPS outputs at the slew rate programmed by the exter-
nal R
tion from boot mode to VID mode.
During startup, the MAX17080 SMPSs are always in
pulse-skipping mode. After exiting the boot mode, the
individual PSI_L bit sets the respective SMPS into
pulse-skipping mode or forced-PWM mode, depending
on the system power state, and adds the +12.5mV off-
set for core supplies if enabled by the OPTION pin. In
combined mode, the PSI_L bit adds the +12.5mV offset
if enabled by the OPTION pin, and switches from
1-phase pulse-skipping mode to 2-phase PWM mode.
Figure 3 is the MAX17080 functional diagram.
The MAX17080 requires an external 5V bias supply in
addition to the battery. Typically, this 5V bias supply is
the notebook’s main 95%-efficient 5V system supply.
Keeping the bias supply external to the IC improves
efficiency and eliminates the cost associated with the
5V linear SMPS that would otherwise be needed to sup-
ply the PWM circuit and gate drivers.
The 5V bias supply powers both the PWM controller
and internal gate-drive power, so the maximum current
drawn is:
where I
table, f
and NB SMPS switching frequencies, Q
24
______________________________________________________________________________________
TIME
SW_CORE
CC
f
I
SW_NB
resistor during VID transitions and the transi-
BIAS
is provided in the Electrical Characteristics
= I
Q
and f
CC
G_NB
+5V Bias Supply (V
+ f
Detailed Description
SW_NB
= 50mA to 70mA (typ)
SW_CORE
are the respective core
Q
G_CORE
G_CORE
+
CC
, V
is the
DD
)
gate charge of the external MOSFETs as defined in the
MOSFET data sheets, and Q
2nC. If the +5V bias supply is powered up prior to the
battery supply, the enable signal (SHDN going from low
to high) must be delayed until the battery voltage is
present to ensure startup.
Connect a resistor (R
set the switching frequency (per phase):
A 71.4kΩ to 432kΩ resistor corresponds to switching fre-
quencies of 600kHz to 100kHz, respectively, for the core
SMPSs, and 1.2MHz to 200kHz for the NB SMPS. High-
frequency (600kHz) operation for the core SMPS opti-
mizes the application for the smallest component size,
trading off efficiency due to higher switching losses. This
might be acceptable in ultra-portable devices where the
load currents are lower and the controller is powered
from a lower voltage supply. Low-frequency (100kHz)
operation offers the best overall efficiency at the
expense of component size and board space.
The NB SMPS runs at twice the switching frequency of
the core SMPSs. The low power of the NB rail allows for
higher switching frequencies with little impact on the
overall efficiency.
Minimum on-time (t
eration when selecting a switching frequency. See the
Core Switching Frequency description in the SMPS
Design Procedure section.
The MAX17080 interleaves both core SMPSs’ phases—
resulting in 180° out-of-phase operation that minimizes
the input and output filtering requirements, reduces
electromagnetic interference (EMI), and improves effi-
ciency. The high-side MOSFETs do not turn on simulta-
neously during normal operation. The instantaneous
input current is effectively reduced by the number of
active phases, resulting in reduced input-voltage ripple,
effective series resistance (ESR) power loss, and RMS
ripple current (see the Core Input Capacitor Selection
section). Therefore, the controller achieves high perfor-
mance while minimizing the component count—which
reduces cost, saves board space, and lowers compo-
nent power requirements—making the MAX17080 ideal
for high-power, cost-sensitive applications.
Interleaved Multiphase Operation
f
SW
= 300kHz × 143kΩ/R
ON(MIN)
Switching Frequency (OSC)
OSC
) between OSC and GND to
) must be taken into consid-
G_NB
is approximately
OSC