MAX17080GTL+ Maxim Integrated Products, MAX17080GTL+ Datasheet - Page 43

• Manufacturer Part Number: MAX17080GTL+
• Description: IC CONTROLLER AMD SVI 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17080GTL+

• Applications: Controller, AMD SVI
• Voltage - Input: 2.7 ~ 5.5 V
• Number Of Outputs: 3
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

Figure 12. SVI Bus Acknowledge
Figure 13. SVI Bus Data Transfer Summary
The SVI bus is not busy when both data and clock lines
remain high. Data transfers can be initiated only when
the bus is not busy. Figure 12 shows the SVI bus
acknowledge.
Starting from an idle bus state (both SVC and SVD are
high), a high-to-low transition of the data (SVD) line while
the clock (SVC) is high determines a START condition.
All commands must be preceded by a START condition.
A low-to-high transition of the SDA line while the clock
(SVC) is high determines a STOP condition. All opera-
tions must be ended with a STOP condition.
DATA OUTPUT
DATA OUTPUT
BY MAX17080
BY MASTER
SVC FROM
MASTER
______________________________________________________________________________________
START
CONDITION
S
START
S
FIXED VALUES
Start Data Transfer (S)
Stop Data Transfer (P)
SLAVE ADDRESS
CLK1
D7
1
Bus Not Busy
AMD 2-/3-Output Mobile Serial
CLK2
D6
2
After generating a START condition, the bus master
transmits the slave address consisting of a 7-bit device
code (110xxxx) for the MAX17080. Since the
MAX17080 is a write-only device, the eighth bit of the
slave address is 0. The MAX17080 monitors the bus for
its corresponding slave address continuously. It gener-
ates an acknowledge bit if the slave address was true
and it is not in a programming mode.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the high period of the clock signal. The data
on the line must be changed during the low period of
the clock signal. There is one clock pulse per bit of data.
SET DAC AND PSI_L
NOT ACKNOWLEDGE
ACKNOWLEDGE
CLK8
D0
8
VID Controller
ACKNOWLEDGE
CLOCK PULSE
CLK9
STOP
9
P
SVD Data Valid
Slave Address
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