FAN5236QSC Fairchild Semiconductor, FAN5236QSC Datasheet - Page 13

• Manufacturer Part Number: FAN5236QSC
• Description: IC CTRLR DDR/PWM DUAL HE 28QSOP
• Manufacturer: Fairchild Semiconductor

Specifications of FAN5236QSC

• Applications: Controller, Mobile-Friendly DDR
• Voltage - Input: 5 ~ 24 V
• Number Of Outputs: 2
• Voltage - Output: 0.9 ~ 5 V
• Operating Temperature: -10°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• Operating Temperature Range: - 10 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FAN5236QSC_NL; FAN5236QSC_NL

FAN5236
Frequency Loop Compensation
Due to the implemented current mode control, the modulator
has a single pole response with -1 slope at frequency deter-
mined by load
where R
For this type of modulator, Type 2 compensation circuit is
usually sufficient. To reduce the number of external compo-
nents and simplify the design task, the PWM controller has
an internally compensated error amplifier. Figure 13 shows a
Type 2 amplifier and its response along with the responses of
a current mode modulator and of the converter. The Type 2
amplifier, in addition to the pole at the origin, has a zero-pole
pair that causes a flat gain region at frequencies between the
zero and the pole.
This region is also associated with phase ‘bump’ or reduced
phase shift. The amount of phase shift reduction depends the
width of the region of flat gain and has a maximum value of
90°. To further simplify the converter compensation, the
modulator gain is kept independent of the input voltage varia-
tion by providing feed-forward of VIN to the oscillator ramp.
The zero frequency, the amplifier high frequency gain and
the modulator gain are chosen to satisfy most typical appli-
cations. The crossover frequency will appear at the point
where the modulator attenuation equals the amplifier high
frequency gain. The only task that the system designer has to
complete is to specify the output filter capacitors to position
the load main pole somewhere within one decade lower than
the amplifier zero frequency. With this type of compensation
plenty of phase margin is easily achieved due to zero-pole
pair phase ‘boost’.
REV. 1.1.9 7/12/04
18
14
0
F
F
P
Z
modulator
F
PO
=
O
=
is load resistance, C
------------------- -
2 R
------------------- -
2 R
=
V
IN
1
--------------------- -
2 R
1
F
2
2
P0
C
C
2
Figure 13. Compensation
1
1
O
C
=
R1
=
REF
O
600kHz
6kHz
R2
F
Z
O
C2
C1
is load capacitance.
EA Out
F
P
(8a)
(8b)
(7)
Conditional stability may occur only when the main load
pole is positioned too much to the left side on the frequency
axis due to excessive output filter capacitance. In this case,
the ESR zero placed within the 10kHz...50kHz range gives
some additional phase ‘boost’. Fortunately, there is an oppo-
site trend in mobile applications to keep the output capacitor
as small as possible.
If a larger inductor value or low ESR values are called for by
the application, additional phase margin can be achieved by
putting a zero at the LC crossover frequency. This can be
achieved with a capacitor across across the feedback resistor
(e.g. R5 from Figure 5) as shown below.
The optimal value of C(Z) is:
Protection
The converter output is monitored and protected against
extreme overload, short circuit, over-voltage and under-
voltage conditions.
A sustained overload on an output sets the PGx pin low and
latches-off the regulator on which the fault occurs. Operation
can be restored by cycling the VCC voltage or by toggling
the EN pin.
If VOUT drops below the under-voltage threshold, the regu-
lator shuts down immediately.
Over-Current sensing
If the circuit’s current limit signal (“ILIM det” as shown in
Figure 11) is high at the beginning of a clock cycle, a pulse-
skipping circuit is activated and HDRV is inhibited. The
circuit continues to pulse skip in this manner for the next 8
clock cycles. If at any time from the 9
cycle, the “ILIM det” is again reached, the over-current
protection latch is set, disabling the regulator. If “ILIM det”
does not occur between cycle 9 and 16, normal operation is
restored and the over-current circuit resets itself.
C Z
=
Figure 14. Improving Phase Margin
----------------------------------------------------- -
L OUT
L(OUT)
VSEN
R
R5
R6
C OUT
C(Z)
PRODUCT SPECIFICATION
VOUT
C(OUT)
th
to the 16
th
clock
(9)
13