NCP5331FTR2G ON Semiconductor, NCP5331FTR2G Datasheet - Page 28

• Manufacturer Part Number: NCP5331FTR2G
• Description: IC CTLR PWM 2PH W/DRVRS 32-LQFP
• Manufacturer: ON Semiconductor

Specifications of NCP5331FTR2G

• Applications: Controller, AMD Athlon™
• Voltage - Input: 9 ~ 14 V
• Number Of Outputs: 2
• Voltage - Output: 5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCP5331FTR2G; NCP5331FTR2GOSTR

copper clad circuit boards will have approximate thermal
resistances (q
should be performed to insure the design will dissipate the
required power under worst case operating conditions.
Variables considered during testing should include
maximum ambient temperature, minimum airflow, maximum
input voltage, maximum loading, and component variations
(i.e., worst case MOSFET R
capacitors share the MOSFET’s heatsinks and will add heat
and raise the temperature of the circuit board and MOSFET.
For any new design, its advisable to have as much heatsink
area as possible − all too often new designs are found to be
too hot and require redesign to add heatsinking.
6. Adaptive Voltage Positioning
Voltage Positioning, R
no−load “high” voltage position and R
full−load “droop” voltage.
pin of the controller. At no load, this resistor will conduct the
internal bias current of the V
drop from V
regulates V
V
condition is shown in Figure 33.
voltage increase above the VID setting (DV
CORE
For TO−220 and TO−263 packages, standard FR−4
As with any power design, proper laboratory testing
There are two resistors that determine the Adaptive
Resistor R
To calculate R
, will be higher by the amount IBIAS
CORE
FB
F1
SA
is connected between V
to the DAC setting, the output voltage,
) as shown in the following table.
(in
Pad Size
0.75/484
2.0/1290
2.5/1612
F1
0.5/323
1.0/645
1.5/968
to the V
2
/mm
the designer must specify the no−load
2
F1
)
FB
and R
DS(on)
pin. Because the error amplifier
L1
0 A
L2
0 A
FB
Single−Sided
1 oz. Copper
pin and develop a voltage
R
R
60−65 C/W
55−60 C/W
50−55 C/W
45−50 C/W
38−42 C/W
33−37 C/W
DRP
). Also, the inductors and
S1
S2
C
C
. R
S1
S2
DRP
CORE
F1
Figure 33. AVP Circuitry at No−Load
CS1
CS2
CS
establishes the
VFB
determines the
NO−LOAD
REF
and the V
R
+
−
+
−
G
G
F1
http://onsemi.com
VDRP
VDRP
. This
) and
NCP5331
FB
V
28
V
CORE
DRP
determine the V
increase is specified in the design guide for the processor
that is available from the manufacturer. The V
is determined by the value of the resistor from R
ground (see Figure TBD for a graph of IBIAS
R
V
be at the DAC voltage so this resistor will conduct zero
current. However, at full−load, the voltage at the V
will increase proportional to the output inductor’s current
while V
will be conducted from V
will be large enough to supply the V
a voltage drop from V
converter’s output voltage will be reduced. This condition is
shown in Figure 34.
the full−load voltage reduction from the VID (DAC) setting
(DV
the V
reduction is specified in the design guide for the processor
that is available from the manufacturer. To predict the
voltage increase at the V
designer must consider the output inductor’s resistance
(R
points (R
sense to the V
R DRP +
from the VID (DAC) setting. DV
voltage change from the no−load AVP setting.
I
OSC
FB
= VID
DRP
COMP
= VID + IBIAS
Resistor R
To determine the value of R
The value of R
DV
L
), the PCB trace resistance between the current sense
CORE,FULL−LOAD
pins. At no−load, the V
). The value of R
R
DRP
CORE,FULL−LOAD
= 0
DV DRP + I O,MAX @ (R L ) R PCB ) @ G VDRP
DRP
FB
Error
Amp
PCB
(IBIAS VFB ) DV CORE,FULL−LOAD R F1 )
pin at full−load. Usually, the full−load voltage
will still be regulated to the DAC voltage. Current
R F1 + DV NO−LOAD IBIAS VFB
V
+
−
FB
), and the controller IC’s gain from the current
DRP
DRP
VFB
= VID
FB
I
DRP
FBK
is connected between the V
pin (G
VID Setting
bias current. Usually, the no−load voltage
w R
IBIAS
= IBIAS
R
F1
can then be calculated.
) and predict the voltage increase at
+ −
F1
F1
is the full−load voltage reduction
VFB
DRP
FB
VDRP
can then be calculated.
DRP
DV DRP
DRP
V
VFB
to V
CORE
pin at full−load (DV
DRP
to V
).
CORE,FULL−LOAD
and the V
CORE
the designer must specify
FB
FB
by R
bias current and cause
across R
DRP
FB
FB
pins will both
. This current
DRP
bias current
VFB
F1
DRP
is not the
DRP
and the
OSC
versus
− the
), the
(29)
(30)
(31)
pin
to