NCP5331 ON Semiconductor, NCP5331 Datasheet

Page 1

... Two−Phase PWM Controller with Integrated Gate Drivers The NCP5331 is a second−generation, two−phase, buck controller that incorporates advanced control functions to power 64−bit AMD Athlont processors and low voltage, high current power supplies. Proprietary multiphase architecture guarantees balanced load−current ...

Page 2

... NCP5331 PIN CONNECTIONS LQFP− DRP LGND 3 22 CS1 REF CS2 FFB REF http://onsemi.com 2 GL1 GND1 GH1 CB OUT V CCH GH2 GND2 GL2 ...

Page 3

... Recommended Components: Q1, Q4: ON Semiconductor NTD60N03 ( 6.1 mW) Q5 Q9: ON Semiconductor NTD80N02 ( 5.0 mW) L1, L2: Coiltronics CTX22−15274 or T50−8B/ #16 AWG Bifilar (1 mW) L3: Coiltronics CTX15−14771 or T30− #16 AWG Figure 1. Application Diagram 1 200 kHz for 64−Bit AMD Athlon Processor NCP5331 CCL1 CCL2 CCL ID4 ...

Page 4

... OVC CCL CCH CCLx GHx 20 V GLx 16 V GND1, GND2 0.3 V LGND 0 V −SEN 0.3 V NCP5331 Rating qJA V I MIN −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V 1.5 A for 1.0 ms, − ...

Page 5

... System Accuracy Shutdown Time Delay Input Threshold VID Pin Bias Current VID Pin Clamp Voltage NCP5331 (0 C < T < < T < 125 C; 9.0 V < 32.4 kW 1.0 nF, C ROSC COMP 5V(REF) Test Conditions Measure V Measure V = COMP SEN = LGND = COMP, −SEN = LGND FB − − ...

Page 6

... Overcurrent Shutdown Timer Overcurrent Shutdown Voltage Threshold C Low Output Voltage OVC C Source Current OVC 1. Guaranteed by design. Not tested in production. 2. The V Bias Current changes with the value NCP5331 (0 C < T < < T < 125 C; 9.0 V < 32.4 kW 1.0 nF, C ROSC COMP 5V(REF) Test Conditions − ...

Page 7

... Offset Measure V OUT Maximum V Voltage 10 mV DRP V FB Current Sense Amp DRP Gain Guaranteed by design. Not tested in production. NCP5331 (0 C < T < < T < 125 C; 9.0 V < 32.4 kW 1.0 nF, C ROSC COMP Test Conditions = 0.22 mF. Note REF until GL1 and GL2 switch High. ...

Page 8

... GATEs not switching, COMP not charging CCH Reference Output 5 V Output Voltage 0 mA < I(5 V REF Internal Ramp Ramp Height @ 50% PWM CS1 = CS2 = CS Duty Cycle 4. Guaranteed by design. Not tested in production. NCP5331 (0 C < T < < T < 125 C; 9.0 V < 32.4 kW 1.0 nF, C ROSC COMP 5V(REF) Test Conditions ...

Page 9

... Power Good output. Open collector output that will transition Low when CS regulation Input power for the CB SB should be connected this pin must be connected to the NCP5331 controller’s internal voltage reference ( Sets the threshold for current limit. Connect to reference through a resistive divider. This pin’s maxi- LIM mum working voltage is 3.0 Vdc. 32 COMP Output of the error amplifier and input for the PWM comparators ...

Page 10

... NCP5331 Non−Overlap Non−Overlap Figure 2. Block Diagram, Control Functions http://onsemi.com 10 ...

Page 11

... NCP5331 Figure 3. Block Diagram, Protection http://onsemi.com 11 ...

Page 12

... Figure 7. Maximum Frequency vs. V NCP5331 NCP5331 5.0 V Controller 25 mA ID4 0. 1.65 V − Value Figure 6. V OSC SOURCE Minimum NCP5331 Pulse Width = 280 SOURCE V (V) CORE http://onsemi.com Value, kW OSC Current vs. R Value FB OSC CORE 80 ...

Page 13

... Temperature ( C) Figure 10. CSA to I Gain vs. Temperature LIM 11.0 10.8 10.6 10.4 10.2 10.0 9.8 9.6 9 Temperature ( C) Figure 12. V Bias Current vs. Temperature FB NCP5331 5.15 5.10 5.05 5.00 4.95 4.90 4. Figure 9. 5 − Figure 11 Figure 13 ...

Page 14

... Overview The NCP5331 dc/dc controller utilizes an Enhanced V topology to meet requirements of low voltage, high current loads with fast transient requirements. Transient response has been improved and voltage jitter virtually eliminated by including an internal PWM ramp, connecting fast−feedback from V directly to the internal PWM comparator, and CORE precise routing and grounding inside the controller ...

Page 15

... Figure 15. Enhanced V Control Employing Lossless Inductive Current Sensing and Internal Ramp with higher current, the PWM cycle will terminate earlier providing negative feedback. The NCP5331 provides a CSx input for each phase, but the CS and COMP inputs are REF common to all phases. Current sharing is accomplished by ...

Page 16

... RLx was used as a sense resistor (RSx). When choosing or designing inductors for use with inductive sensing, tolerances and temperature effects should NCP5331 be considered. Cores with a low permeability material or a large gap will usually have minimal inductance change with temperature and load. Copper magnet wire has a temperature coefficient of 0 ...

Page 17

... COMP Discharge Threshold and then charged back up above the Channel Start Up Offset. Figure 18 shows the NCP5331 operating in hiccup mode with the converter output shorted to GND. Hiccup mode will continue until the overcurrent timer terminates operation. The overcurrent timer sets a limit to how long the converter will operate in hiccup mode ...

Page 18

... V OUT during UVLO. Also, the CB adequate gate drive to enhance the lower MOSFET. The OVP circuits in the NCP5331 are not effected when the ATX supply current limits and V Figure 23 document successful operation of the CB circuitry when an upper MOSFET is shorted during normal operation with 0 A and 45 A loading ...

Page 19

... NCP5331 NOTE: The NCP5331 maintains V < 2.2 V when an upper MOSFET shorts with 45 A loading. Figure 23. NCP5331 Prevents Overvoltage CORE NOTE: The NCP5331 maintains V upper MOSFET is shorted and ATX power is applied. Figure 24. NCP5331 Prevents Overvoltage at Startup Figure 25 ...

Page 20

... When CORE 87.5% DAC, or greater than 2.0 V the open−collector power good pin (PGD) will be pulled low by the NCP5331. When V CORE impedance. An external pull−up resistor is required on PGD. determine the DRP During soft start, when V threshold, 87.5% DAC, then the “longer” of two timers will dictate when PGD becomes high impedance ...

Page 21

... Limit” feature, the Covc pin will again time out and the is CORE NCP5331 will not be able to be turned on after the time out has occurred. This too can be avoided by the use of a transistor at the Covc pin keeping it low while the part is disabled ...

Page 22

... Power Dissipation NCP5331 power dissipation may be approximated by the following equation: P loss + F SW · (V CCH · Q THighFETs ) V CCLx · Q TLowFETs ) ) P Quiescent where: P Quiescent + V CCL · I CCL ) 2 · V CCLx ·I CCLx ) (V CCH ) · I CCH F is the switching frequency CCL V is the low−side gate drive voltage and may be varied CCLx between 5 ...

Page 23

... The capacitors for the current feedback networks should be placed as close to the current sense pins as practical. After placing the NCP5331 control IC, follow these guidelines to optimize the layout and routing: 1. Place the 1 mF ceramic power−supply bypass ...

Page 24

... Therefore necessary to start a design with slightly more than the minimum number of bulk capacitors and perform transient testing or careful modeling/simulation to determine the final number of bulk capacitors. NCP5331 2. Output Inductor Selection The output inductor may be the most critical component in the converter because it will directly effect the choice of other components and dictate both the steady− ...

Page 25

... ON and charge when the control FET is OFF as shown in Figure 30. The following equations will determine the maximum and minimum currents delivered by the input capacitors. I C,MAX + I Lo,MAX IN,AVG I C,MIN + I Lo,MIN IN,AVG I is the maximum output inductor current. Lo,MAX NCP5331 (3.1) I C,MAX (3.2) I C,MIN 0 A −I ...

Page 26

... CORE,FULL−LOAD + CORE,NO−LOAD ) (I O,MAX 2) @ ESR OUT N OUT The differential voltage across the output inductor will cause its current to increase linearly with time. The slew rate of this current can be calculated from NCP5331 SWNODE Lo 729 nH V ...

Page 27

... DS(on) applied gate drive voltage the post gate threshold portion of the switch gate−to−source charge plus the gate−to−drain charge. This may be specified in the data sheet or approximated from the gate−charge curve as shown in the Figure 32. NCP5331 V GS_TH GS1 GS2 Figure 32 ...

Page 28

... VID setting ( NCP5331 determine the V increase is specified in the design guide for the processor that is available from the manufacturer. The V is determined by the value of the resistor from R ground (see Figure TBD for a graph of IBIAS R ). The value of R OSC Resistor R V pins. At no− ...

Page 29

... V DRP CORE Figure 35. V Tuning, RC Time Too Long DRP NOTE: The RC time constant of the current sense network is too short (fast); V and V DRP CORE Figure 36. V tuning, RC Time Too Short DRP NCP5331 CS1 + COMP + − − G VDRP Error S1 Amp R DRP CS2 ...

Page 30

... V CORE and monotonically settles to its final value. Figure 40. COMP Tuning, Bandwidth Optimal NCP5331 8. Error Amplifier Tuning After the steady−state (static) AVP has been set and the current sense network has been optimized the Error Amplifier must be tuned. Basically, the gain of the Error ...

Page 31

... COMP data sheet, Int_Ramp is the internal ramp value at the corresponding duty cycle, Ext_Ramp is the peak−to−peak external steady−state ramp NCP5331 G CSA Startup Offset is typically 0.60V. 12. Power Good Delay Time ), the I SENSE LIM The power good timer sets the delay time between when ...

Page 32

... Input Capacitor Selection Use Equation 5 to determine the average input current to the converter at full−load. I IN,AVG + I O,MAX @ (1.163 0.80 + 6.30 A NCP5331 Next, use Equation 6 to Equation 10 with the full−load inductance value of 729 nH. O,MAX OUT ) @ D ( ( ...

Page 33

... For the upper MOSFET we choose two (1) NTD60N03 and for the lower MOSFETs we choose two (2) NTD80N02, both are from ON Semiconductor. The following parameters are derived from the data sheets. NCP5331 Parameter 1.5 A for 1.0 ms Gate Drive Current Upper Gate Voltage Lower Gate Voltage ...

Page 34

... DRP DV DRP R DRP + (IBIAS VFB ) DV CORE,FULL−LOAD 254 mV (7 3.6 kW) + 14.7 kW NCP5331 7. Current Sensing Choose the current sense network (R satisfy Equation 32 will be most accurate for better iron powder core material (such as the −8 from Micrometals). This material is very consistent with dc current and frequency. ...

Page 35

... D = 1.225 V/ 0.102 OUT ) Ext_Ramp + ( 1.225 V) + 0.102 @ (10 0 200 kHz) + 5.5 mV NCP5331 5 V Figure 42. Setting the Current Limit Then calculate the steady−state COMP voltage. ), LIM2 V COMP + V OUT @ Channel_Startup_Offset can be calculated Finally, solve Equation 35 for the soft−start capacitor and substitute as required ...

Page 36

... BSC S1 4.500 BSC 0.177 BSC V 9.000 BSC 0.354 BSC V1 4.500 BSC 0.177 BSC W 0.200 REF 0.008 REF AE X 1.000 REF 0.039 REF AE ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NCP5331/D ...