NCP5331FTR2G ON Semiconductor, NCP5331FTR2G Datasheet - Page 21

• Manufacturer Part Number: NCP5331FTR2G
• Description: IC CTLR PWM 2PH W/DRVRS 32-LQFP
• Manufacturer: ON Semiconductor

Specifications of NCP5331FTR2G

• Applications: Controller, AMD Athlon™
• Voltage - Input: 9 ~ 14 V
• Number Of Outputs: 2
• Voltage - Output: 5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCP5331FTR2G; NCP5331FTR2GOSTR

0.25 V and “timing out” at 3 V. The current delivered to the
C
according to the following equation.
connecting the C
delay time to the internal delay of 200 ms. Figure 26
demonstrates the use of the programmable PGD timer (set
to 6.0 ms) to allow PGD to transition high when V
safely within the regulation limits for the processor (DAC
Implementing an Enable Function
in one of two ways. The first method (Method A in
Figure 27) is to pull low on the Ilim pin. This method is the
preferred method, as both the GHx and the GLx pins will be
50 mV).
PGD
The programmed delay time can be calculated from
The programmable timer may be disabled (set to 0) by
An Enable function may be implemented on the NCP5331
t PGD + C PGD @ (PGD THRESH * PGD MIN ) I PGD
Hi to Disable
Lo to Enable
*Needed if using ‘Timed
Hiccup Mode Current Limit’
capacitor (I
+ C PGD @ (3.0 V * 0.25 V) I PGD
Figure 27. Enable Method A
PGD
I PGD + 0.52 V R OSC
PGD
pin to 5 V
) is a function of the R
1
REF
3
2
I
LIM
QI
BSS123
. This will set the PGD
LIM
1
C
3
2
OVC
*QC
BSS123
OSC
OVC
CORE
resistor
http://onsemi.com
NCP5331
is
21
kept low at turn−off, preventing V
below ground.
Limit” feature with Method A, the Covc pin will time out
when the Ilim pin is pulled low, and the NCP5331 will not
turn back on (after time out) unless the power is recycled.
This can be avoided by adding another transistor to the Covc
pin, thereby keeping it low while the part is disabled.
on the NCP5331’s comp pin. With this method, GHx will be
low and GLx will be high while the part is disabled.
turn−on, and if using the “Timed Hiccup Mode Current
Limit” feature, the Covc pin will again time out and the
NCP5331 will not be able to be turned on after the time out
has occurred. This too can be avoided by the use of a
transistor at the Covc pin keeping it low while the part is
disabled.
a 1.0 K resistor must be added between the drain of the
transistor and the Comp pin to prevent the current limit from
being tripped when the Comp pin is quickly pulled low.
However, if using the “Timed Hiccup Mode Current
The second method (Method B in Figure 28) is to pull low
However, under Method B, if the part is disabled at
If using Method B but not with a transistor at the Covc pin,
**Allows Disabling at Turn−On
*Needed if not using QCovc
Hi to Disable
Lo to Enable
(when using ‘Timed Hiccup Mode Current Limit’)
Figure 28. Enable Method B
1
COMP
CORE
3
2
QCOMP
BSS123
*R
1.0 k
from being pulled
1
C
3
2
OVC
**QC
BSS123
OVC