XCF128XFTG64C Xilinx Inc, XCF128XFTG64C Datasheet - Page 6
![IC PROM SRL 128M GATE 64-FTBGA](/photos/7/31/73183/xcf128xftg64c_sml.jpg)
XCF128XFTG64C
Manufacturer Part Number
XCF128XFTG64C
Description
IC PROM SRL 128M GATE 64-FTBGA
Manufacturer
Xilinx Inc
Datasheet
1.XCF128XFTG64C.pdf
(88 pages)
Specifications of XCF128XFTG64C
Memory Size
128Mb
Programmable Type
In System Programmable
Voltage - Supply
1.7 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TBGA
Access Time
85ns
Supply Voltage Range
1.7V To 2V
Memory Case Style
FTBGA
No. Of Pins
64
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Package /
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1578
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XCF128XFTG64C
Manufacturer:
XILINX
Quantity:
319
Part Number:
XCF128XFTG64C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
X-Ref Target - Figure 6
Notes:
1.
Write Protect (WP)
Write Protect is an input that gives an additional hardware
protection for each block. When Write Protect is at V
Lock-Down is enabled, and the protection status of the
Locked-Down blocks cannot be changed. When Write
Protect is at V
Locked-Down blocks can be locked or unlocked.
DS617 (v3.0.1) January 07, 2010
Product Specification
See the FT64/FTG64 package specifications at http://www.xilinx.com/support/documentation/package_specifications.htm.
G
C
D
H
A
B
E
F
R
IH
, the Lock-Down is disabled, and the
DQ8
A22
A0
A1
A2
A3
1
K
L
Figure 6: FT64 Package Connections (Top View through Package)
DQ1
DQ0
V SS
WP
NC
A5
A6
A4
2
DQ10
V DD
DQ9
DQ2
A10
A7
A8
A9
3
Platform Flash XL High-Density Configuration and Storage Device
IL
, the
www.xilinx.com
V DDQ
V SSQ
DQ11
V PP
DQ3
A11
RP
4
E
Reset (RP)
The Reset input provides a hardware reset of the memory.
When Reset is at V
outputs are high impedance, and the current consumption is
reduced to the Reset supply current I
blocks are in the Locked state, and the Configuration
Register is reset. When Reset is at V
normal operation. Exiting reset mode the device enters the
synchronous read mode and the FALS is executed.
DQ12
DQ13
DQ4
DQ5
A12
A13
A14
NC
5
V DD
DQ6
V SS
NC
NC
NC
NC
NC
6
IL
, the memory is in reset mode: the
DQ15
DQ14
DQ7
A17
A18
A19
A15
NC
7
IH
DD2
READY_WAIT
, the device is in
. After Reset all
A21
A20
A16
NC
NC
8
W
G
DS617_10_110807
6