XCF128XFTG64C Xilinx Inc, XCF128XFTG64C Datasheet - Page 49

• Manufacturer Part Number: XCF128XFTG64C
• Description: IC PROM SRL 128M GATE 64-FTBGA
• Manufacturer: Xilinx Inc

Specifications of XCF128XFTG64C

• Memory Size: 128Mb
• Programmable Type: In System Programmable
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Access Time: 85ns
• Supply Voltage Range: 1.7V To 2V
• Memory Case Style: FTBGA
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Package /: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1578

X-Ref Target - Figure 27
Notes:
1.
2.
3.
4.
5.
X-Ref Target - Figure 28
DS617 (v3.0.1) January 07, 2010
Product Specification
READY_WAIT
DQ15–DQ0
The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.
The READY_WAIT signal can be configured to be active during wait state or one cycle before. READY_WAIT signal is active Low.
Address latched and data output on the rising clock edge.
Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge of K is the rising one.
The minimum system clock period is T
A22–A0
K
R
W
(4)
G
E
L
Hi-Z
Hi-Z
High
T
ELKH
VALID ADDRESS
Address
T
AVLH
Latch
T
Figure 27: Synchronous Burst Read AC Waveforms, CR4 = 0
AVKH
T
T
ELTV
T
LLKH
T
KHKL
KHAX
T
LLLH
KHQV
X Latency
plus the FPGA data setup time.
Figure 28: Clock Input AC Waveform
T
T
GLQX
GLTV
T
Note 1
F
T
KLKH
Note 2
Platform Flash XL High-Density Configuration and Storage Device
T
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KHKH
T
KHQV
VALID
T
T
KHTV
R
Valid Data Flow
VALID
T
KHTX
T
Note 2
KHQX
VALID
DS617_25_032708
NOT VALID
Boundary
Crossing
Note 2
Valid
Data
T
T
GHQX
GHQZ
VALID
DS617_22_053008
T
Standby
EHEL
T
EHTZ
T
T
EHQX
EHQZ
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