XCF128XFTG64C Xilinx Inc, XCF128XFTG64C Datasheet - Page 12

• Manufacturer Part Number: XCF128XFTG64C
• Description: IC PROM SRL 128M GATE 64-FTBGA
• Manufacturer: Xilinx Inc

Specifications of XCF128XFTG64C

• Memory Size: 128Mb
• Programmable Type: In System Programmable
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Access Time: 85ns
• Supply Voltage Range: 1.7V To 2V
• Memory Case Style: FTBGA
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Package /: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1578

Command Interface
All Bus Write operations to the memory are interpreted by
the Command Interface. Commands consist of one or more
sequential Bus Write operations. An internal Program/Erase
Controller handles all timings and verifies the correct
execution of the program and erase commands. The
Program/Erase Controller provides a Status Register whose
output can be read at any time to monitor the progress or the
result of the operation.
The Command Interface is set to synchronous read mode
when power is first applied, when exiting from Reset, or
whenever V
Command sequences must be followed exactly — any invalid
combination of commands are ignored.
Table 6
Table 6: Command Codes
Read Array Command
The Read Array command returns the addressed bank to
Read Array mode. One Bus Write cycle is required to issue
the Read Array command. After a bank is in Read Array
mode, subsequent read operations output data from the
memory array.
DS617 (v3.0.1) January 07, 2010
Product Specification
Hex Code
01h
03h
10h
20h
2Fh
40h
50h
60h
70h
80h
90h
98h
B0h
BCh
C0h
CBh
D0h
E8h
FFh
provides a summary of the Command Interface codes.
DD
Block Lock Confirm
Set Configuration Register Confirm
Alternative Program Setup
Block Erase Setup
Block Lock-Down Confirm
Program Setup
Clear Status Register
Block Lock Setup, Block Unlock Setup, Block Lock
Down Setup and Set Configuration Register Setup
Read Status Register
Buffer Enhanced Factory Program Setup
Read Electronic Signature
Read CFI Query
Program/Erase Suspend
Blank Check Setup
Protection Register Program
Blank Check Confirm
Program/Erase Resume, Block Erase Confirm,
Block Unlock Confirm, Buffer Program or Buffer
Enhanced Factory Program Confirm
Buffer Program
Read Array
R
falls below its power-down threshold.
Command
Platform Flash XL High-Density Configuration and Storage Device
www.xilinx.com
A Read Array command can be issued to any bank while
programming or erasing in another bank. If the Read Array
command is issued to a bank currently executing a program
or erase operation, the bank returns to Read Array mode
but the program or erase operation continues; however the
data output from the bank is not guaranteed until the
program or erase operation finishes. The read modes of
other banks are not affected.
Read Status Register Command
The device contains a Status Register used to monitor
program or erase operations.
The Read Status Register command is used to read the
contents of the Status Register for the addressed bank. One
Bus Write cycle is required to issue the Read Status
Register command. After a bank is in Read Status Register
mode, subsequent read operations output the contents of
the Status Register.
The Status Register data is latched on the falling edge of
Chip Enable or Output Enable. Either Chip Enable or Output
Enable must be toggled to update the Status Register data.
The Read Status Register command can be issued at any
time, even during program or erase operations. The Read
Status Register command only changes the read mode of
the addressed bank. The read modes of other banks are not
affected. Only Asynchronous Read and Single
Synchronous Read operations should be used to read the
Status Register.
A Read Array command is required to return the bank to
Read Array mode.
See
Register Bits.
Read Electronic Signature Command
The Read Electronic Signature command is used to read the
Manufacturer and Device Codes, Lock Status of the
addressed bank, Protection Register, and Configuration
Register. One Bus Write cycle is required to issue the Read
Electronic Signature command. After a bank is in Read
Electronic Signature mode, subsequent read operations in
the same bank output the Manufacturer Code, Device Code,
Lock Status of the addressed bank, Protection Register, or
Configuration Register (see
The Read Electronic Signature command can be issued at any
time, even during program or erase operations, except during
Protection Register Program operations. Dual operations
between the Parameter bank and the Electronic Signature
location are not allowed (see
If a Read Electronic Signature command is issued to a bank
executing a program or erase operation, the bank enters
Table 11, page 23
for the description of the Status
Table 10, page
Table 17, page 36
22).
for details).
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