XCF128XFTG64C Xilinx Inc, XCF128XFTG64C Datasheet - Page 7

• Manufacturer Part Number: XCF128XFTG64C
• Description: IC PROM SRL 128M GATE 64-FTBGA
• Manufacturer: Xilinx Inc

Specifications of XCF128XFTG64C

• Memory Size: 128Mb
• Programmable Type: In System Programmable
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Access Time: 85ns
• Supply Voltage Range: 1.7V To 2V
• Memory Case Style: FTBGA
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Package /: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1578

Latch Enable (L)
Latch Enable latches the address bits on its rising edge.
The address latch is transparent when Latch Enable is at
V
The Latch Enable (L) signal must be held at V
power-up phase, during the FALS restart phase and
through the entire FALS.
In asynchronous mode, the address is latched on L going
High. or addresses are sent continuously if L is held Low.
During Write operations, L can be tied Low (V
addresses to flow through.
Table 3: Latch Enable Logic Levels in Synchronous
and Asynchronous Modes
Clock (K)
The Clock input synchronizes the memory to the FPGA
during synchronous read operations. The address is
latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at V
ignored during asynchronous read and in write operations.
Ready/Wait (READY_WAIT)
READY_WAIT can perform one of two functions. By default,
READY_WAIT is an input/open-drain ready signal
coordinating the initiation of the device's synchronous read
operation with the start of an FPGA configuration sequence.
Optionally, READY_WAIT can be dynamically configured as
an output wait signal, indicating a wait condition during a
synchronous read operation.
Upon a power-on reset (POR) or RP-pin reset event, the
device drives READY_WAIT to V
initiate a synchronous read or receive a command. When the
device reaches an internal ready state from a reset condition,
READY_WAIT is released to a high-impedance state (an
external pull-up resistor to V
DS617 (v3.0.1) January 07, 2010
Product Specification
Notes:
1.
IL
Address Latch
and inhibited when Latch Enable is at V
Caution!
resistor to V
sufficiently strong to ensure a clean, Low-to-High transition
within less than one microsecond (T
READY_WAIT pin is released to a high-impedance state.
See waveforms in the
details.
Operation
Bus Read
Bus Write
Power-up
Standby
Reset
FALS
R
The READY_WAIT requires an external pull-up
DDQ
. The external pull-up resistor must be
Asynchronous
X or toggling
"DC and AC Parameters"
Toggling
V
V
V
DDQ
X
X
IH
IH
IH
IL
is required to externally pull
until the device is ready to
RWRT
Synchronous
X or toggling
) when the
Toggling
IH
IL
.
section for
V
V
V
V
IH
) to allow the
X
IH
IH
IH
IH
IL
during the
. Clock is
Platform Flash XL High-Density Configuration and Storage Device
www.xilinx.com
the READY_WAIT signal to a valid input High). The device
waits until the READY_WAIT input becomes a valid input
High before permitting a synchronous read or accepting a
command. Connecting the READY_WAIT to the FPGA
INIT_B pin in a wired-and circuit creates a handshake
coordinating the initiation of the device synchronous read
with the start of the FPGA configuration sequence.
When READY_WAIT is an input/open-drain ready signal, the
system can drive READY_WAIT to V
synchronous read operation. A valid address must be provided
to the device for a reinitiated synchronous read operation.
Optionally, READY_WAIT can be configured as an output
signaling a wait condition during a synchronous read
operation. The wait condition indicates a clock cycle during
which the output data is not valid. When configured as an
output wait signal, READY_WAIT is high impedance when
Chip Enable is at V
configured as a wait signal, READY_WAIT can be configured
to be active during the wait cycle or one clock cycle in
advance, and the READY_WAIT polarity can be configured.
V
V
memory device and is the main power supply for all
operations (Read, Program and Erase).
V
V
all outputs to be powered independently of V
V
V
by the voltage range applied to the pin.
If V
seen as a control input. In this case a voltage lower than
V
while V
only sampled at the beginning of a program or erase — a
change in its value after the operation starts does not have
any effect, and all program or erase operations continue.
If V
supply pin. In this condition V
Program/Erase algorithm is completed.
V
V
be connected to the system ground.
V
V
driven by V
Note:
decoupled with a 0.1 μF ceramic capacitor close to the pin (high-
frequency, inherently low-inductance capacitors should be placed
PP
DD
DDQ
PPLK
SS
SSQ
DD
DDQ
PP
SS
SSQ
PP
PP
is either a control input or a power supply pin, selected
Ground is the reference for the core supply and must
provides the power supply to the internal core of the
Program Supply Voltage
Ground
Supply Voltage
Ground is the reference for the input/output circuitry
provides the power supply to the I/O pins and enables
is kept in a low voltage range (0V to V
is in the range of V
gives absolute protection against program or erase,
Each device in a system should have V
PP
Ground
Supply Voltage
in the V
DDQ
. V
PP1
SSQ
IH
or Output Enable is at V
range enables these functions. V
must be connected to V
PPH
, the signal acts as a power
PP
must be stable until the
IL
to reinitiate a
DD
DDQ
, V
IH
DD
SS
. Only when
DDQ
.
), V
.
and V
PP
PP
is
PP
is
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