IDT71P71804S200BQG8 IDT, Integrated Device Technology Inc, IDT71P71804S200BQG8 Datasheet - Page 15

• Manufacturer Part Number: IDT71P71804S200BQG8
• Description: IC SRAM 18MBIT 200MHZ 165FBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT71P71804S200BQG8

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 18M (1M x 18)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 71P71804S200BQG8

JTAG Block Diagram
This part contains an IEEE standard 1149.1 Compatible Test Access
Port (TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during
manufacturing and system diagnostics. In conformance with IEEE 1149.1,
the SRAM contains a TAP controller, Instruction register, Bypass Regis-
ter and ID register. The TAP controller has a standard 16-state machine
that resets internally upon power-up; therefore, the TRST signal is not
TAP Controller State Diagram
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
1
0
TDI
TMS
TCK
Test Logic Reset
Run Test Idle
0
1
1
1
1
Capture DR
Update DR
Select DR
Pause DR
Exit 1 DR
Exit 2 DR
Shift DR
Identification Reg.
Instruction Reg .
Control Signal s
BYPASS Reg.
TAP Controller
0
0
1
0
1
1
0
SRAM
CORE
1
0
0
0
1
6112 drw 18
1
Capture IR
Update IR
Select IR
Pause IR
Exit 1 IR
Exit 2 IR
Shift IR
0
0
1
1
0
1
1
6112 drw 17
TDO
1
0
0
0
0
6.42
15
required. It is possible to use this device without utilizing the TAP. To
disable the TAP controller without interfacing with normal operation of the
SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and
TDI are designed so an undriven input will produce a response identical
to the application of a logic 1, and may be left unconnected, but they may
also be tied to VDD through a resistor. TDO should be left unconnected.
NOTE:
1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM
2. TDI is sampled as an input to the first ID register to allow for the serial shift of
3. Bypass register is initialized to Vss when BYPASS instruction is invoked.
4. SAMPLE instruction does not place output pins in Hi-Z.
5. This instruction is reserved for future use.
JTAG Instruction Coding
IR2
The Bypass Register also holds serially loaded TDI when exiting the Shift DR
0
0
0
0
states.
1
1
1
1
the external TDI data.
inputs.
IR1
0
0
0
0
1
1
1
1
IR0
0
0
0
0
1
1
1
1
SAMPLE/PRELOAD Boundary Scan register
RESERVED
RESERVED
RESERVED
Instruction
SAMPLE-Z
BYPASS
EXTEST
IDCODE
Commercial Temperature Range
TDO Output
Boundary Scan Register
Identification register
Boundary Scan Register
Do Not Use
Do Not Use
Do Not Use
Bypass Register
6112 tbl 13
Notes
2
5
4
5
5
3
1