IDT71P71804S200BQG8 IDT, Integrated Device Technology Inc, IDT71P71804S200BQG8 Datasheet - Page 13

• Manufacturer Part Number: IDT71P71804S200BQG8
• Description: IC SRAM 18MBIT 200MHZ 165FBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT71P71804S200BQG8

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 18M (1M x 18)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 71P71804S200BQG8

AC Electrical Characteristics
NOTES:
1. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
2. V
3. If C,C are tied High, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. During production testing, the case temperature equals T
8. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).
9. Clock to clock time (tKHKH) and Clock to clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
Clock Parameters
Output Parameters
Set-Up Times
Hold Times
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
KHKH
KC var
KHKL
KLKH
KHKH
KHKH
KHCH
KC lock
KC reset
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CHQZ
CHQX1
AVKH
IVKH
DVKH
KHAX
KHIX
KHDX
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worse case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
Symbol
dd
slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
Clock Cycle Time (K,K,C,C)
Clock Phase Jitter (K,K,C,C)
Clock High Time (K,K,C,C)
Clock LOW Time (K,K,C,C)
Clock to clock (K→K,C→C)
Clock to data clock (K→C,K→C)
DLL lock time (K, C)
K static to DLL reset
C,C HIGH to output valid
C,C HIGH to output hold
C,C HIGH to echo clock valid
C,C HIGH to echo clock hold
CQ,CQ HIGH to output valid
CQ,CQ HIGH to output hold
C HIGH to output High-Z
C HIGH to output Low-Z
Data-in and BWx valid to K, K rising edge
K,K rising edge to address hold
K,K rising edge to R, W inputs hold
K, K rising edge to data-in and BWx hold
Clock to clock (K→K,C→C)
Address valid to K,K rising edge
R, W inputs valid to K,K rising edge
Parameter
A.
(V
DD
1
is bigger than tCHQZ.
1024
-0.45
-0.45
-0.30
-0.45
Min.
4.00
1.60
1.60
1.80
1.80
0.00
0.50
0.50
0.40
0.50
0.50
0.35
= 1.8 ± 100mV, V
30
-
-
-
-
-
250MHz
6.42
13
6.30
0.20
0.50
0.50
0.30
0.45
Max
1.80
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DDQ
-0.45
-0.45
-0.35
-0.45
Min.
5.00
2.00
2.00
2.20
2.20
0.00
1024
0.60
0.60
0.40
0.60
0.60
0.40
30
-
-
-
-
-
= 1.4V to 1.9V, T
200MHz
7.88
0.20
2.30
0.50
0.50
0.35
0.45
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A
Commercial Temperature Range
-0.50
-0.50
-0.40
-0.50
Min.
1024
6.00
2.40
2.40
2.70
2.70
0.00
0.70
0.70
0.50
0.70
0.70
0.50
=0 to 70°C)
30
-
-
-
-
-
167MHz
Max
8.40
0.20
2.80
0.50
0.50
0.40
0.50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(3,7)
cycles
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6112 tbl 11
Notes
3,4,5
3,4,5
1,5
8
8
9
9
2
3
3
3
3
6
6