MT46H16M16LFBF-6 IT:A Micron Technology Inc, MT46H16M16LFBF-6 IT:A Datasheet - Page 68

• Manufacturer Part Number: MT46H16M16LFBF-6 IT:A
• Description: IC DDR SDRAM 256MBIT 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H16M16LFBF-6 IT:A

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 100mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant
• Other names: Q3368612

Figure 39:
Figure 40:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
All DQ values, collectively
Command
DQS or LDQS/UDQS
Data Output Timing –
Data Input Timing
CK#
CK
Notes:
Notes:
READ
T0
2
1
1. DQ transitioning after DQS transition define
2. All DQ must transition by
3.
4. Shown with CL = 3.
1.
2.
3. WRITE command issued at T0.
4. For x16, LDQS controls the lower byte, and UDQS controls the upper byte. For x32, DQS0
5. For x16, LDM controls the lower byte, and UDM controls the upper byte. For x32, DM0 con-
t
t
t
controls DQ[7:0], DQS1 controls DQ[15:8], DQS2 controls DQ[23:16], and DQS3 controls
DQ[31:24].
trols DQ[7:0], DM1 controls DQ[15:8]5, DM2 controls DQ[23:16], and DM3 controls
DQ[31:24].
AC is the DQ output window relative to CK and is the long-term component of DQ skew.
DSH (MIN) generally occurs during
DSS (MIN) generally occurs during
NOP
T1
CL = 3
DQS
t
DM
DQ
CK#
AC and
CK
4
5
6
t AC (MAX)
NOP
T2
t DQSCK
t RPRE
(MAX)
t
DQSCK
T0
t DQSS
3
T2n
t
t WPRES
DQSQ after DQS transitions, regardless of
68
T2
t DS
NOP
T3
t WPRE
t
t
T2n
DQSS (MAX).
DQSS (MIN).
D
T1
b
IN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3n
t DSH
256Mb: x16, x32 Mobile DDR SDRAM
t DH
Transitioning data
t DQSCK
(MAX)
T1n
1
T3
t
t DQSL
DQSQ window.
t DSS
NOP
T4
2
T3n
T2
t DQSH t WPST
t DSH
T4n
T2n
1
T4
t DSS
NOP
T5
©2005 Micron Technology, Inc. All rights reserved.
2
T4n
T3
Don’t Care
Timing Diagrams
T5n
t HZ (MAX)
t
AC.
T5
NOP
T6
T5n
t RPST