IS43R16800A-5TL-TR ISSI, Integrated Silicon Solution Inc, IS43R16800A-5TL-TR Datasheet - Page 8

• Manufacturer Part Number: IS43R16800A-5TL-TR
• Description: IC DDR SDRAM 128MBIT 66TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS43R16800A-5TL-TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOPII
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS43R16800A
Notes:
1. All AC parameters measuremed with the following test conditions.
2. This parameter defines the signal transition delay from the crossing point of CK and CK. The signal transition is defined to occur
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal
5. t
6. t
7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal
8. The timing reference level is V
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. There is no specific reference voltage
10. t
11. t
12. VDD is assumed to be 2.6V ± 0.1V. V
13. t
8
when the signal level crosses VTT.
transition is defined to occur when the signal level crosses VTT.
is the crossing point of CK and CK. This parameter is not referred to a specific voltage level, but when the device output stops
driving.
to a specific voltage level, but when the device output begins driving.
transition is defined to occur when the signal level crosses V
to judge this transition.
LZ
HZ
CK
CK
DAL
is defined as the data output transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is referring
is defined as the data output transition delay from Low-Z to High-Z at the end of a read burst operation. The timing reference
(max.) is determined by the locking range of the DLL. Beyond this lock range, the DLL operation is assured.
= t
= (t
CK
WR
(min) when these parameters are measured. Otherwise, absolute minimum values of these values are 10% of t
/t
CK
)+(t
RP
/t
CK
). For each of the add-ins, if not an integer already, round up to the nearest integer.
REF
.
DD
power supply variation per cycle expected to be less than 0.4V per 400 cycles.
REF
.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ISSI
Rev. 00A
07/11/05
CK
.
®